JIT Simulation Code Converter for CPU Performance Prediction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current simulation methods for CPU performance and power simulation, especially those involving pipeline control, are inefficient due to high processing speeds and large code loads, making them unsuitable for practical application, particularly when dealing with complex multicore systems.
Innovation Solution
A simulation apparatus and method that divides program code into blocks, predicts execution timing for externally dependent instructions, and corrects execution times based on prediction results and delay times, generating host code for high-speed performance simulation while reducing code load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If JIT compiler system is adopted for function simulation of target CPU, then processing speed is improved, but simulation accuracy for pipeline control and out-of-order process deteriorates
Solution Approach 1:
The patent segments the simulation process into two distinct phases: a prediction phase that uses JIT compilation for fast execution of instructions, and a correction phase that adjusts the results based on actual pipeline behavior. This segmentation allows the system to benefit from both speed (during prediction) and accuracy (during correction), resolving the contradiction between processing speed and simulation accuracy.
Solution Approach 2:
The patent performs preliminary prediction of instruction execution results using JIT compilation before the actual simulation execution. By predicting the outcomes in advance and then correcting them based on real pipeline behavior, the system achieves both high speed (from preliminary prediction) and high accuracy (from subsequent correction), eliminating the trade-off between these two parameters.
2Reliability
If interpreter system is adopted for CPU simulation, then simulation accuracy is improved, but processing speed deteriorates
Solution Approach 1:
The patent performs preliminary translation of target CPU instructions to host CPU instructions using JIT compilation before execution. This preliminary action enables the system to achieve interpreter-level accuracy while maintaining JIT-level speed, as the translation is done in advance rather than during execution, thus resolving the contradiction between accuracy and speed.
3Speed
If JIT compiler system is adopted for performance simulation of target CPU, then processing speed is improved, but code load increases due to enormous simulation codes
Solution Approach 1:
The patent extracts the simulation codes from the main host code by separating them into a distinct correction phase. Only the necessary correction logic for pipeline effects is included, rather than embedding all possible simulation scenarios into the host code. This extraction reduces code load while maintaining processing speed through efficient correction mechanisms.
Solution Approach 2:
The patent applies partial action by only adding correction codes for specific pipeline effects that actually occur during simulation, rather than including all possible simulation scenarios. This selective approach reduces code load while maintaining sufficient accuracy for performance simulation, resolving the contradiction between speed and code quantity.
Data Source
AI summary
A code converter 11 of a simulation apparatus 1 detects, during the execution of a program in a target CPU, an externally dependent instruction affected by the external environment in each of divided blocks, predicts the execution result of the externally dependent instruction, simulates the instruction execution in the predicted result, and generates a host code in which a code for performance simulation is embedded based on the simulation result. A simulation executor 12 performs performance simulation about instruction execution in the prediction result of the program using the host code, and when the execution result of the externally dependent instruction is different from the setting of the prediction result during the execution, corrects the execution time of the instruction in the prediction result using the execution time of instructions executed before and after the instruction, and the like. A simulation information collector 13 collects and outputs performance simulation information.