JIT Compiler Snippet Tagging for Heterogeneous Processors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In heterogeneous multi-processor systems, existing Just-In-Time (JIT) compilers face challenges in optimizing code execution across processors with different architectures, leading to suboptimal performance and power efficiency, as they cannot effectively utilize hardware-specific characteristics and runtime data to select the most efficient code snippets for execution.
Innovation Solution
A method where a JIT compiler compiles input code into multiple snippets, tags them with specific characteristics, and selects the most suitable ones for execution based on runtime data, including hardware performance counters and bandwidth load measurements, to generate re-compiled snippets that execute efficiently on the appropriate processors, thereby optimizing performance and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single instance of JIT compiler generates code snippets optimized for one processor architecture, then compilation speed is maintained, but execution performance degrades on heterogeneous processors with different micro-architectures
Solution Approach 1:
The patent segments the code generation process by creating multiple processor-specific code snippet instances from a single input code snippet. Each snippet is optimized for a specific processor architecture (e.g., Cortex-A15 vs Cortex-A7), allowing the system to select the most appropriate snippet for each processor type, thereby resolving the conflict between compilation speed and execution performance on heterogeneous processors.
Solution Approach 2:
The patent applies local quality by generating code snippets with architecture-specific optimizations tailored to each processor's micro-architecture characteristics. Each snippet contains local optimizations appropriate for its target processor (e.g., utilizing specific ALU configurations, cache sizes, or pipeline characteristics), enabling high execution performance on each processor type without sacrificing overall compilation efficiency.
2Speed
If the system compiles code snippets for all possible processor configurations, then execution performance on heterogeneous processors is optimized, but compilation time and resource usage increase
Solution Approach 1:
The patent applies preliminary action by pre-generating multiple processor-specific code snippet instances during an initial compilation phase. These snippets are prepared in advance and stored for rapid selection during runtime based on the target processor architecture, avoiding the need for repeated compilation on heterogeneous processors while maintaining optimization benefits.
Solution Approach 2:
The patent changes compilation parameters to generate multiple variants of code snippets with different optimization levels and architecture-specific features. By systematically varying compilation parameters for different target architectures, the system creates a library of pre-optimized snippets that can be quickly selected at runtime, balancing compilation overhead against execution performance.
3Device complexity
If the JIT compiler selects code snippets without considering processor-specific characteristics, then compilation complexity is reduced, but power efficiency and performance optimization are lost
Solution Approach 1:
The patent implements feedback by incorporating runtime information about the executing processor's architecture into the code snippet selection process. The system monitors processor characteristics (such as architecture type, performance state, and operational characteristics) and uses this feedback to select or generate appropriately optimized code snippets, thereby achieving power efficiency without excessive compilation complexity.
Solution Approach 2:
The patent applies dynamics by making the code snippet selection process adaptive to runtime conditions. Instead of static selection, the system dynamically chooses snippets based on current processor state, architecture characteristics, and operational context, enabling power-efficient execution while keeping the compilation mechanism relatively simple through runtime adaptation.
4Speed
If multiple compiled code snippets are generated and stored for each input code snippet, then execution efficiency on specific processors is improved, but memory usage and system resources increase
Solution Approach 1:
The patent extracts only the essential processor-specific variations into separate code snippet instances, rather than duplicating entire code bases for each processor. By extracting and storing only the architecture-critical differences in multiple snippet versions, the system achieves execution efficiency on heterogeneous processors while minimizing the memory overhead associated with maintaining multiple code versions.
Data Source
AI summary
A method in a Just-In-Time, JIT, compiler for compiling code in a JIT-compiler for a heterogeneous multiprocessor system is provided. The method comprises compiling a snippet of input code, whereby one or more compiled code snippets are generated for the snippet of input code. The one or more compiled code snippets are tagged with one or more snippet specific characteristics. One or more compiled code snippets are selected from the compiled code snippets, based on said snippet specific characteristics. The one or more selected compiled code snippets are executed on one or more of the plurality of processors. While executing, run-time data is gathered, where the gathered data is tagged for which processor in the heterogeneous multiprocessor system it is related to.