Jitter-Attenuated Clock for Asynchronous Node Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital communication systems face challenges in managing jitter and synchronizing asynchronous nodes, leading to bit errors and dropped packets, especially in voice payload transmissions over packet networks.
Innovation Solution
A method is introduced to dynamically acquire integer derivatives of a gapped clock frequency, which is used within a phase-locked loop for jitter attenuation, enabling synchronizer/desynchronizer functions and complex mapping/demapping protocols in communication applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous timing is used in Ethernet nodes, then each node operates independently with local timing sources, but timing mismatches accumulate causing bit errors and packet drops
Solution Approach 1:
The patent introduces a timing intermediary mechanism that extracts timing information from the Ethernet data stream itself. The receiver uses the embedded isochronous timing information in the data stream to slave its timing to the transmitter's timing source, creating a mediator that bridges the timing between asynchronous nodes without requiring external synchronization infrastructure.
2Reliability
If synchronous timing distribution is used, then timing synchronization is maintained across the network, but timing jitter and wander from transport paths exceed acceptable limits
Solution Approach 1:
The patent extracts the timing signal from the synchronous SONET/SDH transport path and embeds it directly into the Ethernet data stream. By taking out the timing information from the hierarchical synchronous network and embedding it in the Ethernet payload, the system maintains timing synchronization while avoiding the accumulation of jitter and wander that occurs in traditional synchronous transport.
Solution Approach 2:
The patent creates a copy of the transmitter's timing signal and embeds it within the Ethernet data stream as isochronous timing information. This timing copy travels with the data through the network, allowing the receiver to synchronize to the exact same timing source as the transmitter, effectively replicating the timing relationship without relying on external synchronous distribution.
3Adaptability or versatility
If pointer processing is used in SONET, then plesiochronous payloads are embedded in synchronous frames, but implementation becomes increasingly difficult in FPGAs and ASICs as data rates increase
Solution Approach 1:
The patent replaces the complex mechanical pointer processing system with a simplified digital embedding approach. Instead of using physical pointer adjustments and frame slips to handle plesiochronous payloads, the system embeds timing information directly in the data stream and uses digital signal processing to resynchronize, eliminating the need for complex pointer processing hardware.
Data Source
AI summary
A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.