Jitter Buffer Clock Compensation for Network Latency

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Solution Overview

Problem

Voice Over Packet (VOP) systems experience degradation in audio quality due to disruptions in the temporal pattern of audio packets as they travel through packet networks, primarily caused by varying network latency and clock differentials, which existing jitter buffer techniques struggle to accurately compensate for.

Innovation Solution

A Jitter Buffer Module (JBM) with a circular buffer and variable readout position is implemented, using a Clock Compensation Module to dynamically adjust packet delays based on statistical analysis of network latency and clock differentials, ensuring proper sequencing and synchronization of audio packets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If audio packets are transmitted through a packet network, then network communication capability is improved, but temporal pattern disruption occurs causing audio quality degradation

Engineering Contradiction:
Improvenetwork communication capabilityVSAvoidaudio quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary actions by measuring and recording network latency values before audio packet transmission, building a latency profile that is used to pre-calculate compensation delays. This allows the temporal pattern disruption to be compensated for in advance rather than reactively, maintaining audio quality while enabling packet network transmission.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by continuously measuring network latency, building profiles of latency characteristics, and using this information to dynamically adjust packet delay compensation. The measured latency values feed back into the compensation mechanism, creating a closed-loop system that adapts to changing network conditions and maintains temporal pattern integrity.

Inventive Principle:
Principle #23Feedback

2Reliability

If existing jitter buffer techniques are used to compensate for network latency, then some temporal pattern recovery is achieved, but accurate compensation for clock differentials is insufficient

Engineering Contradiction:
Improvetemporal pattern recoveryVSAvoidclock differential compensation accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The system replaces traditional mechanical clock synchronization mechanisms with a software-based compensation approach. Instead of physically synchronizing clocks between sender and receiver, the system measures latency variations and calculates compensation delays algorithmically, substituting mechanical precision requirements with computational processing.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system changes parameters by dynamically adjusting packet delay compensation based on measured latency values and calculated clock differentials. Rather than using fixed compensation values, the system modifies delay parameters in real-time based on observed network conditions and statistical analysis of latency profiles.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If packet delay compensation is increased to maintain temporal pattern, then audio quality is improved, but network latency is amplified

Engineering Contradiction:
Improveaudio qualityVSAvoidnetwork latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system applies dynamics by making packet delay compensation adaptive rather than static. The compensation amount varies dynamically based on measured latency values and calculated clock differentials, allowing the system to apply minimal necessary delay in stable conditions and increased delay only when network variations require it, thus balancing audio quality with latency optimization.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7450593B2Clock difference compensation for a network
Publication Date: 2008.11.11 INTEL CORP
  • US7450593B2 patent drawing
  • US7450593B2 patent drawing
  • US7450593B2 patent drawing

AI summary

A method and apparatus to perform clock compensation for a jitter buffer are described.