Jitter Buffer Controller Sequence Number Skipping
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Solution Overview
Problem
Conventional jitter buffering techniques face challenges in synchronizing system clocks between transmitter and receiver, leading to under-running issues and communication errors, especially in facsimile and audio communications over IP networks, due to precision differences and packet loss, which can result in transmission delays and errors.
Innovation Solution
A jitter buffer control apparatus and method that includes a buffer with a controller responsive to under-running, skipping storage locations associated with packet loss to prevent output during under-running periods and manage sequence numbers, thereby minimizing communication errors and transmission delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a predetermined volume of data is stored in the reception jitter buffer prior to commencing output to prevent under-running, then under-running is prevented, but transmission delay increases
Solution Approach 1:
The patent applies preliminary action by storing a predetermined volume of data in the reception jitter buffer before commencing output. This ensures that the buffer is adequately filled to prevent under-running during operation, thereby improving reliability while accepting the trade-off of increased transmission delay.
2Reliability
If the storage capacity of the reception jitter buffer is increased to reduce under-running, then under-running is reduced, but transmission delay increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the storage capacity of the reception jitter buffer based on operating conditions. The buffer capacity is increased when under-running is detected or anticipated, and decreased when stable conditions prevail, thereby reducing under-running while minimizing transmission delay through adaptive parameter adjustment.
3Reliability
If packet loss compensation means generates a pseudo linear signal based on past input signal, then packet loss is compensated, but modem signal phase is disarranged causing reception error
Solution Approach 1:
The patent applies the taking out principle by extracting and isolating the packet loss compensation function from the main signal processing path. The pseudo linear signal generation is performed separately based on past input signals, and the compensated signal is integrated only when necessary, thereby preventing phase disarrangement in the modem signal while maintaining packet loss compensation capability.
4Reliability
If the reception jitter buffer stores data corresponding to 140 ms prior to output, then under-running is prevented, but communication error increases due to phase disarrangement
Solution Approach 1:
The patent applies dynamics by making the jitter buffer storage duration adaptive rather than fixed. The buffer stores data corresponding to a predetermined time period before output, but this duration is dynamically adjusted based on actual operating conditions such as packet loss rates and clock synchronization status. This allows the system to prevent under-running while minimizing the risk of communication errors through flexible, condition-based adjustment of the storage duration.
Data Source
AI summary
A jitter buffer control apparatus has a buffer for storing data included in an input packet transmitted from a telecommunications network, and a jitter buffer controller for controlling the buffer to store the input data into the buffer and take out the stored data from the buffer on the basis of a sequence number included in the input packet in a processing period. When under-running occurs in the buffer, the jitter buffer controller stores input data into the buffer with a storage location skipped which corresponds to the processing period associated with packet loss due to the under-running.