Jitter Producing Circuitry for SERDES Tolerance Testing

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Solution Overview

Problem

Current automatic test equipment is inadequate for producing serial data signals with jitter, making it difficult to test the jitter tolerance of serializer/deserializer (SERDES) circuitry and other receiver circuitry.

Innovation Solution

Introducing jitter into a serial data signal by varying the clock signal's timing, allowing for controllable frequency and amplitude of jitter, which can be used to test the jitter tolerance of circuitry without modifying the automatic test equipment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If known automatic test equipment is used to test SERDES circuitry, then production testing can be performed, but the equipment cannot produce serial data signals with jitter, making it impossible to test jitter tolerance

Engineering Contradiction:
Improvejitter tolerance testing capabilityVSAvoidsignal generation capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

A jitter injection circuit is introduced as an intermediary component between the test equipment and the device under test. This circuit receives a clean clock signal and deliberately adds controlled jitter to it, then feeds the jittered signal to the SERDES circuitry under test. This mediator enables the test equipment to indirectly generate jittered signals without requiring direct modification of the equipment itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The jitter characteristics are pre-configured in the jitter injection circuit before actual testing begins. Parameters such as jitter amplitude, frequency, and type (random, periodic, deterministic) are set in advance through programming or hardware configuration. This preliminary setup allows the test system to rapidly switch between different jitter conditions without real-time adjustments during testing.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the automatic test equipment is modified to generate jittered signals, then jitter tolerance testing becomes possible, but the complexity and cost of the equipment increases

Engineering Contradiction:
Improvejitter tolerance testing capabilityVSAvoidtest equipment structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The jitter generation functionality is extracted from the main test equipment and placed in a separate, dedicated jitter injection circuit. This modular approach allows the core test equipment to remain simple and unchanged, while the extracted jitter injection module handles all complexity related to signal degradation. The separated module can be independently designed, tested, and replaced without affecting the main equipment.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If jitter is added to the clock signal to create jittered data signals, then realistic testing conditions are achieved, but the difficulty of controlling and characterizing the jitter increases

Engineering Contradiction:
Improvetesting accuracyVSAvoidjitter control and characterization
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The jitter injection circuit incorporates feedback mechanisms that continuously monitor the generated jitter characteristics and compare them against target values. Based on this feedback, the circuit automatically adjusts its internal parameters to maintain precise control over jitter amplitude, frequency, and temporal distribution. This closed-loop control ensures that the injected jitter accurately represents real-world conditions while remaining precisely measurable and repeatable.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7849370B2Jitter producing circuitry and methods
Publication Date: 2010.12.07 MARVELL ISRAEL (M L S L) LTD
  • US7849370B2 patent drawing
  • US7849370B2 patent drawing
  • US7849370B2 patent drawing

AI summary

To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).