Digital Jitter Detector Using Delay Chain Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits experience unpredictable jitter in clock signals due to various sources, making it difficult for designers to accurately assess and manage jitter levels, which can impact operating frequency and performance.
Innovation Solution
A jitter detector system comprising a logic circuit and clocked storage devices that identify and accumulate errors in a delay chain's outputs over multiple clock cycles, allowing for precise measurement of jitter levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If designers use ideal clock signal assumptions in design, then design simplicity is maintained, but actual jitter measurement accuracy is insufficient
Solution Approach 1:
The detection system is segmented into multiple delay elements that create distinct time delays for different signal paths. Each delay element captures jitter at different time points, allowing the system to measure jitter magnitude by comparing which delay element's output is captured in error by the clocked storage device.
Solution Approach 2:
A delay chain acts as an intermediary between the clock signal source and the detection logic. The delay chain transforms the jitter measurement problem into a detectable error condition by creating time-skewed versions of the clock signal that can be compared against expected timing relationships.
2Productivity
If designers increase operating frequency to improve performance, then productivity increases, but jitter-related errors increase
Solution Approach 1:
The system performs preliminary jitter characterization during design and manufacturing by measuring which delay element outputs are captured in error. This preliminary measurement provides data about actual jitter levels, allowing designers to determine safe operating frequencies before the circuit begins production operation, ensuring reliability at the desired productivity level.
Solution Approach 2:
The clocked storage device provides feedback about timing errors by capturing incorrect values when jitter exceeds acceptable thresholds. This feedback mechanism identifies when operating frequency is too high for the actual jitter conditions, allowing frequency adjustment to maintain reliable operation.
3Reliability
If designers design for maximum expected jitter, then reliability is improved, but operating frequency must be reduced
Solution Approach 1:
The system changes the parameter being measured from theoretical jitter specifications to actual empirical jitter measurements. By measuring real jitter levels in the manufactured circuit using the delay chain and error detection mechanism, designers can adjust operating frequency based on actual performance rather than conservative estimates, optimizing the reliability-productivity tradeoff for each specific circuit instance.
Data Source
AI summary
In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic circuit is configured to identify a first input of the plurality of inputs that is: (i) captured in error from a corresponding one of the plurality of outputs of the delay chain, and (ii) the corresponding one of the plurality of outputs of the delay chain is least delayed by the delay chain among the plurality of outputs that are captured in error. The plurality of clocked storage devices are configured to accumulate an indication of which of the plurality of outputs have been captured in error over a plurality of clock cycles of the first clock input.