Jitter Filtering Circuit for High-Speed Serial I/O Testing
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Solution Overview
Problem
Conventional testing apparatuses for evaluating high-speed and multi-lane serial I/O interfaces are costly and inflexible, requiring complex clock recovery circuits and high-speed sampling, making them unsuitable for low-cost, high-volume production testing and difficult to adapt for multi-channel devices.
Innovation Solution
A testing apparatus with a jitter filtering circuit that extracts and filters jitter components from output signals, using a variable delay circuit to control the phase of the output signal and remove jitter, allowing for evaluation without a clock recovery circuit, and including a comparator and timing generating section to assess the device-under-test based on phase control and timing signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a real-time sampling oscilloscope is used to accurately measure edge timings and sample at high speed, then measurement precision is improved, but apparatus cost increases
Solution Approach 1:
The invention extracts only the necessary timing information from the data signal by detecting edge transitions and measuring their timings, rather than using a full real-time sampling oscilloscope system. This extraction approach achieves the required measurement precision while avoiding the high cost and complexity of complete real-time sampling equipment.
Solution Approach 2:
The invention creates a simplified measurement system that copies only the essential functionality needed for eye opening measurement - specifically, the timing detection and comparison capabilities - rather than implementing a complete real-time oscilloscope system. This allows achieving measurement goals with reduced apparatus cost.
2Measurement precision
If a real-time sampling oscilloscope with digital signal processing is used, then measurement precision is improved, but loss of time increases due to lengthy analysis
Solution Approach 1:
The invention performs preliminary processing by detecting edge timings and comparing them against expected values in advance, preparing the data for eye opening calculation. This preliminary action reduces the computational burden and analysis time while maintaining measurement precision.
Solution Approach 2:
The invention extracts only the essential timing information needed for eye opening measurement - the actual edge timings and their comparison with expected timings - rather than performing complete digital signal processing on the entire data signal. This extraction approach significantly reduces analysis time while preserving measurement accuracy.
3Measurement precision
If a clock recovery circuit is used to recover clock and re-sample data signal, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The invention extracts timing information directly from the data signal by detecting edge transitions, rather than using a complete clock recovery circuit to regenerate the clock signal. This extraction approach achieves the necessary timing measurement precision while avoiding the complexity of clock recovery circuits including phase-locked loops and other synchronization components.
4Measurement precision
If a real-time sampling oscilloscope is used, then measurement precision is improved, but adaptability decreases for multi-channel devices
Solution Approach 1:
The invention creates a universal measurement system that can handle both single-channel and multi-channel devices through the same basic architecture. By using parallel processing of timing detections and comparisons for multiple channels, the system achieves multi-channel adaptability while maintaining the measurement precision of the single-channel approach.
Data Source
AI summary
There is provided a testing apparatus for evaluating a device-under-test, having an extracting section for extracting jitter components out of an output signal outputted out of the device-under-test, a filter for passing predetermined frequency components in the jitter components, a phase control section for controlling phase of the output signal based on the jitter components outputted out of the filter and an evaluating section for evaluating the device-under-test based on a signal outputted out of the phase control section.