Jitter Measurement Circuit Using On-Chip Delay Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional jitter measurement methods face challenges due to limited pin counts on chips, signal distortion, and the need for external testing equipment, which affects accuracy and resolution, especially in high-speed data transmission systems.
Innovation Solution
A device and method for jitter measurement that includes a signal retrieving module, signal amplifying module, edge detecting module, and time-to-digital converting module, which amplifies pulse width to improve resolution and converts it to a digital signal without requiring additional reference signals, allowing for built-in self-testing and multiple resolution settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional off-chip jitter measurement methods are used with oscilloscope or spectrum analyzer, then measurement capability is provided, but measurement precision deteriorates due to signal distortion from I/O pads and bonding wirings
Solution Approach 1:
The patent extracts the jitter measurement function from external testing equipment and implements it directly within the chip using built-in self-testing circuits. The I/O pad and bonding wiring are excluded from the measurement path by using on-chip delay lines and signal processing, eliminating the source of signal distortion and improving measurement accuracy.
Solution Approach 2:
The chip performs its own jitter measurement through built-in self-testing functionality. The device under test generates test signals and measures its own output jitter using on-chip delay lines and signal processing circuits, eliminating the need for external oscilloscopes or spectrum analyzers and reducing testing complexity.
2Adaptability or versatility
If pin count is increased to provide more testing access, then more signals can be measured independently, but mechanical limitation of packaging technology prevents pin count from increasing proportionally with transistor number
Solution Approach 1:
The built-in self-testing circuits enable existing I/O pins to serve dual purposes: normal data transmission and jitter measurement. The same pins used for serial transmission are also used to output test signals and carry measurement data, eliminating the need for dedicated test pins and maximizing the utility of limited pin resources.
Solution Approach 2:
The patent merges the test signal generation, transmission, and measurement functions into a single integrated system that operates through the existing serial transmission infrastructure. The delay lines and signal processing circuits are combined with the normal data path, allowing measurement without requiring separate test signal paths or additional pins.
3Device complexity
If serial transmission is used to decrease pin count, then pin usage is optimized, but the method cannot be applied to analog signal and testing difficulty increases for mix-signal chips
Solution Approach 1:
The patent replaces the need for physical analog signal transmission through I/O pads with on-chip digital signal processing. The delay lines and signal processing circuits operate entirely in the digital domain, converting analog measurement requirements into digital logic operations that can be performed using standard CMOS processes and existing digital infrastructure.
Solution Approach 2:
The patent introduces on-chip delay lines as intermediary elements between the output signal and the measurement point. These delay lines provide the necessary time delays for jitter measurement without requiring external analog signal paths, acting as a bridge that enables measurement functionality within the digital domain while maintaining compatibility with serial transmission protocols.
4Measurement precision
If conventional jitter measurement architecture with ring oscillators is used, then time-to-digital conversion is achieved, but chip area increases and load effect is generated
Solution Approach 1:
The patent changes the operating parameters of the delay lines by adjusting their delay values to create the necessary time differences for jitter measurement. Instead of using complex ring oscillator circuits with multiple stages, the invention achieves time-to-digital conversion by precisely controlling and comparing delay parameters through simple logic circuits, significantly reducing the required chip area.
Solution Approach 2:
Instead of using ring oscillators to generate periodic signals and measure phase differences through oscillation counting, the patent inverts the approach by using fixed delay lines with predetermined delay values and measuring the time difference through direct logic comparison. This inversion eliminates the need for oscillating circuits and their associated area requirements while maintaining measurement functionality.
Data Source
AI summary
The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal.