On-Chip Jitter Meter Using Capacitive Charge Accumulation
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Solution Overview
Problem
Conventional methods for measuring phase noise and jitter in phase-locked loops (PLL) and voltage-controlled oscillators (VCO) require external frequency references and large dynamic range subsystems, making them non-autonomous and impractical for high-frequency applications.
Innovation Solution
A jitter meter device that selectively charges a capacitive element using a received signal, with an analog-to-digital converter to determine the accumulated jitter value and phase noise, eliminating the need for external frequency references and reducing analog functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase noise measurement methods are used with external frequency references and large dynamic range subsystems, then measurement accuracy is improved, but device complexity and integration difficulty increase
Solution Approach 1:
The patent extracts and eliminates the need for external frequency references and complex analog subsystems by implementing a fully integrated on-chip measurement solution. The external reference oscillator and complex analog delay lines are removed, replacing them with on-chip digital counters and frequency synthesizers that work with the device under test itself.
Solution Approach 2:
The measurement system uses the device under test (VCO or PLL) itself as the frequency reference by feeding back its own output through a divider. This universal approach eliminates the need for separate external reference sources and allows the same circuit to measure both VCO and PLL phase noise without additional external components.
2Measurement precision
If low noise mixers and long delay lines are used for high frequency measurements, then measurement sensitivity is improved, but integrability on chip deteriorates
Solution Approach 1:
The patent replaces analog mechanical components (mixers, delay lines) with digital electronic components (counters, frequency synthesizers). The measurement is performed in the digital domain using on-chip counters that accumulate phase error over multiple cycles, eliminating the need for long analog delay lines and low-noise mixers that cannot be integrated.
Solution Approach 2:
The patent changes the measurement approach from direct analog phase detection to digital accumulation of phase error over N cycles. By integrating the phase error digitally over multiple cycles, the system achieves high sensitivity without requiring long analog delay lines, enabling full on-chip implementation.
3Measurement precision
If external frequency references with very low phase noise are used, then measurement accuracy is improved, but autonomy deteriorates
Solution Approach 1:
The measurement system is fully autonomous and self-sufficient, using the device under test itself as the frequency reference. The VCO or PLL output is fed back through a divider to provide the reference signal, eliminating the need for external low-phase-noise references and enabling standalone on-chip measurement without external equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables jitter measurement at lower frequencies by storing long-term jitter in a DC voltage using a capacitor, without requiring accurate frequency references or calibrated delay lines, and minimizes analog functionality.
Implementation Method 1
a capacitive element capable of being selectively charged, wherein the selection is made by a received signal from which an accumulated jitter value is to be determined
Data Source
AI summary
A device and method for measuring jitter includes a capacitive element capable of being selectively charged, wherein the selection is made by a received signal from which an accumulated jitter value is to be determined. An analog-to-digital converter is coupled to the capacitive element to determine a voltage across the capacitive element after a number of cycles of the received signal. A determination module is coupled to the analog-to-digital converter to output the accumulated jitter value of the received signal using the voltage, wherein the accumulated jitter value is accumulated over the number of cycles.