Jitter Precorrection Filter for Time-Average Clock Distortion
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Solution Overview
Problem
Time-average-frequency clock generation in electronic systems can cause distortion due to cycle-to-cycle phase modulation, particularly in applications like digital-to-analog converters, where evenly-spaced sample times are assumed, leading to spurious components and noise in high-bandwidth data processing.
Innovation Solution
A jitter precorrection filter, implemented as an all-pass variable delay digital filter, is inserted in the data path of the clock signal to compensate for the effects of varying clock cycle periods, specifically designed to work with flying-adder frequency synthesizers, allowing for digital computation and flexible implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-average-frequency clock generation is used, then clock generation efficiency and robustness are improved, but cycle-to-cycle phase modulation occurs causing distortion
Solution Approach 1:
The patent applies preliminary action by calculating and storing ideal sample values in advance based on expected jitter conditions. The jitter buffer contains pre-computed correction values that are applied before the actual distortion occurs, allowing the system to compensate for phase modulation without real-time computation delays.
Solution Approach 2:
The patent introduces a jitter buffer as an intermediary component between the time-average-frequency clock generator and the digital signal processing pipeline. This buffer acts as a mediator that absorbs and compensates for cycle-to-cycle phase variations, isolating the downstream processing from jitter effects while preserving the efficient clock generation approach.
2Device complexity
If time-average-frequency clock is used, then implementation complexity is reduced, but spurious components and noise increase in high-bandwidth processing
Solution Approach 1:
The system performs preliminary computation of ideal sample values and stores them in a jitter buffer before they are needed. This advance preparation eliminates the need for complex real-time jitter correction algorithms, maintaining simple implementation while effectively reducing spurious components and noise through pre-computed compensation.
Solution Approach 2:
The patent creates a copy of the ideal signal waveform in advance and stores it in the jitter buffer. This copied reference waveform serves as a template for correction, allowing the system to replace distorted samples with pre-computed ideal values without requiring complex real-time processing, thus reducing both implementation complexity and output noise.
3Manufacturing precision
If conventional PLL is used, then each clock period can be precisely controlled, but clock generation efficiency and robustness decrease
Solution Approach 1:
The patent changes the fundamental parameter of clock generation from fixed-period control to time-averaged frequency control. By allowing individual clock periods to vary while maintaining the average frequency precision, the system achieves both high efficiency through simple digital implementation and adequate precision for the application, using the jitter buffer to compensate for period variations.
Solution Approach 2:
The system pre-calculates the ideal clock periods and stores correction values in advance. This preliminary action allows the use of efficient time-average-frequency generation while maintaining effective period control through pre-computed compensation, achieving both productivity and precision goals.
Data Source
AI summary
Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word.