Jitter Test Pattern Generation for 10 GbE Communication Systems
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Solution Overview
Problem
The existing jitter test systems for 10 GbE communication systems require large circuit sizes due to the need for generating and verifying synchronizing signals, CRC, and minimum packet intervals in the jitter test pattern, which increases the complexity and size of the test pattern generation and verification circuits.
Innovation Solution
A communication system based on the OSI Reference Model that separates the processing of frame data into upper layer processing and MAC layer processing, allowing the pattern body generation unit to only generate the payload portion of the jitter test pattern in MAC frame format, and the receiving-end MAC unit to verify the jitter test pattern body without generating or verifying synchronizing signals, CRC, and minimum packet intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the test pattern generation circuit generates a jitter test pattern in MAC frame format including synchronizing signal, CRC, and minimum packet interval, then the jitter test can be performed according to IEEE802.3ae standard, but the circuit size of the test pattern generation circuit increases
Solution Approach 1:
The patent divides the jitter test pattern generation into two independent parts: (1) a test pattern generation circuit that only generates the payload portion (jitter test pattern body), and (2) a MAC layer processing unit that adds the synchronizing signal, CRC, and minimum packet interval. This segmentation allows the test pattern generation circuit to be simplified while the MAC layer handling is standardized, resolving the contradiction between test accuracy and circuit complexity.
Solution Approach 2:
The patent makes the MAC layer processing unit perform dual functions: it processes both normal data frames and jitter test pattern frames through the same MAC layer handling (adding synchronizing signal, CRC, etc.). This multi-functionality eliminates the need for separate specialized circuits for test pattern generation, reducing overall circuit size while maintaining IEEE802.3ae standard compliance.
2Reliability
If the test pattern verification circuit verifies synchronizing signal, CRC, and minimum packet interval in the received jitter test pattern, then the jitter test completeness is ensured, but the circuit size of the verification circuit increases
Solution Approach 1:
The patent extracts the MAC layer processing functions (including synchronizing signal addition, CRC generation, and minimum packet interval insertion) from the specialized test pattern generation circuit and places them in the standard MAC layer processing unit. Consequently, the verification circuit only needs to verify the payload portion, extracting and ignoring the MAC layer overhead, which significantly reduces verification circuit complexity while maintaining test completeness.
Solution Approach 2:
The MAC layer processing unit serves itself by handling both normal frame processing and jitter test pattern processing through the same standardized routines. The verification is performed by comparing the received payload with the originally generated payload, using the same MAC layer processing logic that was applied during transmission, eliminating the need for separate verification circuits for MAC layer elements.
3Adaptability or versatility
If a separate test pattern generation circuit is used to generate jitter test pattern in MAC frame format, then the jitter test can be performed, but the overall device complexity increases
Solution Approach 1:
The patent makes the existing MAC layer processing unit universal by enabling it to handle both normal data transmission and jitter test pattern transmission through the same processing pipeline. The selector switches between normal data input and test pattern body input, but the MAC layer processing (adding synchronizing signal, CRC, etc.) remains the same, eliminating the need for separate test-specific hardware and reducing overall device complexity.
Solution Approach 2:
The patent merges the jitter test pattern generation function with the existing MAC layer processing unit. Instead of having a separate dedicated test pattern generation circuit that creates complete MAC frames, the invention combines the simple payload generation with the existing MAC layer processing, merging two functions into one integrated flow that reduces device structural complexity.
Data Source
AI summary
In a communication system based on OSI (Open Systems Interconnection) Reference Model, a pattern body generation circuit of a transmitting device generates and outputs a jitter test pattern body for jitter test. A selector selects an output (frame data) of a transmitting-end upper circuit during normal communication and selects an output (pattern body) of the pattern body generation circuit during jitter test. A transmitting-end MAC circuit performs transmitting-end processing of a MAC layer on the data selected by the selector to thereby obtain a MAC frame. A receiving-end MAC circuit performs receiving-end processing of a MAC layer on a received frame in MAC frame format to thereby obtain a payload. A pattern body verification circuit verifies a pattern body that is a payload obtained by the receiving-end MAC circuit during jitter test against a corresponding pattern body before transmission.