Data Transmitter Jitter Tolerance Measurement via Bypass Circuit
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Solution Overview
Problem
Conventional data transmitting/receiving devices face difficulties in accurately measuring jitter tolerance due to the filtering effect of internal PLLs in the data analyzer, leading to misrecognized bit errors and incorrect measurement of jitter tolerance.
Innovation Solution
The implementation of a data selection circuit that allows for the selection and transmission of either internal or external parallel data, enabling the measurement of jitter tolerance using serial data by synchronizing the parallel-serial and serial-parallel conversion circuits with the operation clock, and optionally using a clock adjustment circuit to ensure synchronization and reduce bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If jitter tolerance is measured by analyzing parallel data output from the serial-parallel conversion circuit, then the measurement system can process data, but the internal PLL filtering causes misinterpretation of bit errors leading to incorrect jitter tolerance evaluation
Solution Approach 1:
The patent extracts the harmful effect of the internal PLL filtering by separating the measurement path from the normal data processing path. A dedicated measurement mode is introduced where the serial-parallel conversion circuit is bypassed or disabled, allowing direct analysis of serial data without PLL interference. This extraction of the problematic component (PLL filtering) from the measurement process resolves the contradiction between being able to process data and obtaining accurate jitter tolerance measurements.
Solution Approach 2:
The patent introduces a measurement mode as an intermediary state between normal operation and jitter tolerance evaluation. In this intermediary mode, the system switches from processing parallel data through the full conversion chain to directly analyzing serial data with the PLL disabled. This intermediary measurement path serves as a mediator that eliminates the harmful PLL filtering effect while still allowing the measurement system to function.
2Ease of operation
If the serial-parallel conversion circuit processes reception data through internal PLL, then data conversion is achieved, but the PLL filtering interferes with accurate jitter tolerance measurement
Solution Approach 1:
The patent applies dynamics by making the serial-parallel conversion circuit configurable between two operational states: normal mode where the circuit operates with PLL filtering for standard data conversion, and measurement mode where the circuit is disabled or bypassed for accurate jitter tolerance measurement. This dynamic switching capability allows the system to adapt its operation based on the specific task, resolving the contradiction between ease of data conversion operation and measurement precision.
3Reliability
If bit errors are reduced by delaying latch timing by 1/2 cycle, then data extraction reliability is improved, but measurement of jitter tolerance becomes inaccurate due to PLL filtering
Solution Approach 1:
The patent segments the data processing function from the measurement function. The serial-parallel conversion circuit with its delayed latch timing (which ensures reliable data extraction) is separated into the normal processing path, while a distinct measurement path is created that directly analyzes serial data without passing through the conversion circuit. This segmentation allows both functions to operate optimally without interfering with each other.
Data Source
AI summary
The first data transmitting/receiving device according to the present invention includes: a serial-parallel conversion circuit for converting received first serial data to first parallel data; a data selection circuit for selecting any one of the first parallel data and externally-supplied second parallel data and outputting the selected data; and a parallel-serial conversion circuit for converting the first or second parallel data output from the data selection circuit to second serial data which is to be transmitted.