On-Chip Jitter Tolerance Measurement Circuit
Solution Overview
Problem
The high cost and time required for manufacturing integrated circuits due to the need for expensive specialized test equipment to measure jitter tolerance, which is essential for evaluating their noise tolerance and bit-error-ratio performance.
Innovation Solution
On-chip circuits that generate jitter signals with variable amplitude and frequency, allowing for on-chip jitter tolerance measurement, eliminating the need for expensive test equipment and reducing manufacturing time by integrating jitter generator circuits, CDR circuits, and control systems to adjust receive clock signals and compare data values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If expensive specialized test equipment is used to measure jitter tolerance, then measurement precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the jitter signal generation function from external specialized test equipment and implements it within the integrated circuit itself through dedicated jitter generator circuits. This allows the IC to self-test its jitter tolerance without requiring expensive external equipment, thereby reducing manufacturing costs while maintaining measurement precision.
Solution Approach 2:
The integrated circuit performs self-testing by generating its own jitter signals through internal jitter generator circuits and measuring its own jitter tolerance. This self-service approach eliminates the need for external specialized test equipment, reducing both manufacturing cost and test time while maintaining accurate measurement capability.
2Measurement precision
If expensive specialized test equipment is used to measure jitter tolerance, then measurement precision is improved, but manufacturing time increases
Solution Approach 1:
The patent extracts the jitter signal generation function from external specialized test equipment and implements it within the integrated circuit itself through dedicated jitter generator circuits. This allows the IC to self-test its jitter tolerance without requiring expensive external equipment, thereby reducing manufacturing costs while maintaining measurement precision.
Solution Approach 2:
The integrated circuit performs self-testing by generating its own jitter signals through internal jitter generator circuits and measuring its own jitter tolerance. This self-service approach eliminates the need for external specialized test equipment, reducing both manufacturing cost and test time while maintaining accurate measurement capability.
3Ease of manufacture
If on-chip jitter generator circuits are integrated, then device complexity increases, but ease of manufacture improves
Solution Approach 1:
The patent merges the jitter generator circuits, CDR circuits, and measurement functionality into a single integrated circuit package. This consolidation allows the IC to perform self-testing without external equipment, improving manufacturing efficiency by eliminating the need for specialized external test equipment while managing complexity through integration.
Data Source
AI summary
An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.