Jitter Tolerance Testing for Multi-Die Integrated Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for evaluating the jitter tolerance of components within multi-die integrated circuits are not fully effective, as they fail to accurately assess the ability of die components to handle jitter in signaling with other dies.
Innovation Solution
A system and method for minimally invasive jitter tolerance testing, involving a first die with transmitters and a second die with receivers and a performance monitor, where a signal path couples transmit signals and an external pin is used to induce jitter, allowing for the measurement and determination of performance characteristics despite adverse conditions like cross talk or insertion loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional jitter tolerance testing methods are used, then testing can be performed, but the testing is not fully effective and fails to accurately assess the ability of die components to handle jitter
Solution Approach 1:
The patent introduces an intermediary testing signal path that couples the transmit signal from a first die to a receiver on a second die through an intra-package trace. This intermediary path allows for controlled introduction of jitter and measurement of its effects, enabling accurate assessment of jitter tolerance while maintaining reliable testing conditions that mimic actual operational environments.
2Ease of operation
If minimal invasive testing is implemented, then the testing approach is less intrusive, but it requires precise coupling of transmit signals through intra-package traces to external pins
Solution Approach 1:
The patent segments the testing system into distinct functional components: a first die with transmitters, a second die with receivers and performance monitors, and separate signal paths. One path couples transmit signals through intra-package traces to external pins for non-invasive measurement, while another path introduces controlled jitter. This segmentation allows minimal invasive testing while managing complexity through modular organization.
3Reliability
If jitter is induced in transmit signals to test tolerance, then the ability to assess jitter handling is improved, but the presence of jitter creates adverse conditions that may affect signal quality
Solution Approach 1:
The patent applies preliminary anti-action by introducing controlled jitter through a dedicated signal path before the signal reaches the receiver, allowing the system to preemptively assess how the receiver will handle jittered signals. The performance monitor measures error rates under these controlled adverse conditions, enabling accurate jitter tolerance evaluation without causing uncontrolled signal degradation.
Data Source
AI summary
A method of assessing the ability of one or more multi-die circuit elements to tolerate the presence of jitter in intra-package. The method includes: providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter; providing a second die having a set of receivers for digital communications; providing a performance monitor; coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers; coupling a second transmit signal from the second transmitter to an external pin; supplying an input signal that induces jitter in the first and second transmit signals; measuring jitter in the second transmit signal via the external pin; and determining, using the performance monitor, a performance characteristic of the second die.