Jitterless Zone CPU Scheduler for VM Latency
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Solution Overview
Problem
Current CPU resource allocation metrics in virtual machines (VMs) result in significant latency and jitter, which are unsuitable for workloads requiring predictable responsiveness and low latency, such as those in IoT Edge devices and network functions virtualization, especially in the telecommunications industry, where Service Level Agreements (SLAs) demand millisecond or sub-millisecond CPU latency.
Innovation Solution
The implementation of a jitterless zone within a virtual machine (VM) where a CPU scheduler allocates specific physical CPUs to vCPUs based on Quality of Service (QoS) parameters, ensuring predictable resource allocation and minimizing jitter by preempting non-jitterless workloads to maintain low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU resource allocation metrics (reservation, limit, shares) are used to allocate pCPU resources to VMs, then resource utilization is improved and costs are reduced, but significant latency and jitter are introduced that make the system unsuitable for workloads requiring predictable responsiveness
Solution Approach 1:
The patent segments pCPUs into two distinct groups: jitterless pCPUs dedicated to jitterless workloads and non-jitterless pCPUs for other workloads. This segmentation is implemented through a jitterless zone data structure that tracks which pCPUs are available for jitterless scheduling. By separating the CPU pool, the system can guarantee deterministic timing for time-sensitive applications while still allowing aggressive resource sharing and overcommitment for non-time-sensitive workloads, thus resolving the contradiction between high resource utilization and low latency/jitter.
Solution Approach 2:
The patent applies local quality by providing different scheduling guarantees to different workloads based on their requirements. The jitterless scheduling policy is selectively applied only to workloads marked as requiring deterministic timing (via the jitterless workload determination), while other workloads continue to use standard scheduling policies. This allows the system to optimize for low latency where needed while maintaining high overall resource utilization through flexible scheduling elsewhere, resolving the contradiction between predictable responsiveness and resource efficiency.
2Reliability
If physical core pinning is used to dedicate pCPUs to specific vCPUs for guaranteed performance, then CPU QoS requirements are met with predictable latency, but costs increase and resource efficiency is reduced
Solution Approach 1:
The patent implements dynamic pCPU allocation within the jitterless zone through a run-time scheduler that can preempt and migrate jitterless workloads between available jitterless pCPUs based on current system state and workload demands. Unlike static physical core pinning, this dynamic approach allows the system to adapt to changing conditions while maintaining QoS guarantees. The jitterless zone data structure is updated dynamically to reflect current pCPU availability, enabling flexible resource allocation that improves efficiency compared to fixed pinning while preserving reliability through active management of scheduling constraints.
Solution Approach 2:
The patent introduces a jitterless zone data structure and run-time scheduler as intermediaries between the hypervisor and the physical CPUs. This intermediary layer manages the allocation and preemption of pCPUs to jitterless workloads, translating high-level QoS requirements into concrete scheduling decisions. The intermediary maintains the jitterless zone information about which pCPUs are available for jitterless scheduling and coordinates preemptions of non-jitterless workloads to make pCPUs available when needed, thus achieving QoS guarantees without requiring static physical core pinning and the associated efficiency losses.
3Loss of time
If non-jitterless workloads are preempted to allocate pCPUs to jitterless workloads, then latency guarantee is improved for time-sensitive applications, but overall system throughput may be reduced
Solution Approach 1:
The patent applies partial action by preempting non-jitterless workloads only when necessary to allocate pCPUs to jitterless workloads, rather than continuously or excessively. The run-time scheduler monitors the jitterless zone data structure and triggers preemptions only when jitterless pCPUs become unavailable, balancing latency guarantees with throughput maintenance. This selective preemption approach ensures that time-sensitive applications receive the deterministic timing they require while minimizing disruption to overall system throughput by allowing non-critical workloads to continue executing when jitterless scheduling demands are not immediate.
Data Source
AI summary
The disclosure provides techniques for scheduling a jitterless workload on a virtual machine (VM) executing on a host comprising one or more pCPUs comprising a first subset of the one or more pCPUs and a second subset of the one or more pCPUs. The techniques further include creating a jitterless zone, wherein the jitterless zone includes the first subset of the one or more pCPUs. The techniques further include determining whether a vCPU of the VM is used to execute a jitterless workload or a non-jitterless workload. The techniques further include allocating by a CPU scheduler to the vCPU at least one of the pCPUs in the jitterless zone when the vCPU of the VM is used to execute a jitterless workload. The techniques further include scheduling the jitterless workload for execution by the vCPU on the allocated at least one of the pCPUs in the jitterless zone.