Phase Hysteretic Magnetic Josephson Junction Memory Cell
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Solution Overview
Problem
Current superconducting digital technologies face limitations in achieving high integration density and low power dissipation for random-access memory (RAM), which hinders their industrialization, especially in high-end and quantum computing applications, due to fundamental constraints on the size of inductive loops and high power dissipation in cryogenic environments.
Innovation Solution
A Josephson magnetic random access memory (JMRAM) system utilizing phase hysteretic magnetic Josephson junctions with ferromagnetic barriers and directional write elements to store binary states, generating spontaneous supercurrents and orienting them predictably through orthogonal electrical currents, enabling efficient data writing and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional superconducting memory based on inductive loops is used, then high speed operation is achieved, but integration density is fundamentally limited by the size of the inductive loop
Solution Approach 1:
The patent changes the fundamental operating parameter from magnetic flux quantization to superconducting phase control. The PHMJJ operates by switching between different superconducting phases (0 and π states) rather than relying on flux quanta, enabling much smaller device dimensions while maintaining high-speed operation through phase-dependent critical current modulation.
Solution Approach 2:
The invention replaces the mechanical/physical constraint of inductive loop geometry with a quantum mechanical effect - the Josephson effect and superconducting phase control. This substitution allows memory operation without the need for large inductive loops, achieving both high speed and high integration density.
2Reliability
If hybrid CMOS memory with Josephson detection is used, then some performance improvement is achieved, but power dissipation remains relatively high for cryogenic environment
Solution Approach 1:
The patent merges the memory storage function and the detection function into a single integrated superconducting circuit. The PHMJJ simultaneously serves as the storage element (through its phase state) and the detection element (through its phase-dependent critical current), eliminating the need for separate CMOS logic and reducing overall power dissipation in the cryogenic environment.
Solution Approach 2:
The PHMJJ performs self-detection through its intrinsic phase-dependent critical current特性. When the stored phase state (0 or π) changes, it directly modulates the critical current, which can be detected without external CMOS readout circuitry, enabling the memory cell to detect its own state with minimal power consumption.
3Area of stationary object
If phase hysteretic magnetic Josephson junction is used for storage, then integration density is improved, but predictable orientation of spontaneous supercurrent for reliable reading becomes challenging
Solution Approach 1:
The patent introduces an intermediary mechanism - the phase-dependent critical current of the PHMJJ - that mediates between the spontaneous supercurrent (which may have random orientation) and the readout circuit. The critical current acts as a controllable gate that can be modulated by external magnetic fields or currents to enable reliable detection of the stored phase state regardless of spontaneous supercurrent orientation.
Solution Approach 2:
The invention uses parameter changes in the PHMJJ critical current (controlled by external fields or currents) to encode and read the stored phase information. By modulating the critical current parameter based on the stored phase state (0 or π), the system achieves reliable readout while maintaining the benefits of small device size for high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The JMRAM system achieves predictable and reliable data storage with enhanced margins during read operations, ensuring consistent binary state detection and reducing power dissipation, thereby overcoming the limitations of existing superconducting memory technologies.
Implementation Method 1
phase hysteretic magnetic Josephson junction (PHMJJ)...configured to generate a superconducting phase based on the stored digital state
Implementation Method 2
outer layers of superconducting material...generate a spontaneous supercurrent in the conducting loop through the PHMJJ
Implementation Method 3
soft ferromagnetic layer whose magnetization is switchable as a result of magnetic fields generated locally by two orthogonal electrical currents (IRW, IWW) of the write currents
Implementation Method 4
internal thin film layers of ferromagnetic material comprising a hard ferromagnetic layer and a soft ferromagnetic layer
Implementation Method 5
critical current is such that when providing the read current to the PHMJJ in the first binary state, the read current combines with the spontaneous supercurrent generated by the PHMJJ to make a current having a magnitude that is greater than the one of the critical current
Data Source
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AI summary
One embodiment describes a JMRAM memory cell system. The system includes a phase hysteretic magnetic Josephson junction (PHMJJ) that stores one of a first binary state and a second binary state in response to a write current provided during a data write operation and to provide a superconducting phase based on the stored digital state. The system also includes a directional write element configured to provide a directional bias current during the data write operation to provide the superconducting phase of the PHMJJ in a predetermined direction corresponding to the first binary state. The system further includes at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current that is provided during a read operation.