Hardware Accelerator Job Information Cache for Bandwidth Reduction

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Solution Overview

Problem

In networking applications, hardware accelerators often lack sufficient cache or memory to store ancillary information, leading to repeated retrieval from external memory, which reduces system bus bandwidth and hinders performance due to high latency and data transfer requirements.

Innovation Solution

Implementing a data protection architecture that shares common job information among processing units within the hardware accelerator, reducing the need for redundant memory accesses by maintaining shared descriptor segments and utilizing burst transfers to minimize external memory reads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the hardware accelerator repeatedly obtains ancillary information from external memory for each job, then the hardware accelerator can process jobs, but the system bus bandwidth is reduced and performance is hindered

Engineering Contradiction:
Improvejob processing throughputVSAvoidsystem bus bandwidth consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent implements a job information cache within the hardware accelerator that pre-stores ancillary information (cryptographic keys, initialization vectors, protocol information) before jobs are processed. When jobs are received, the cache already contains the necessary ancillary information, eliminating the need for repeated memory accesses during job execution. This preliminary caching action resolves the contradiction by maintaining high productivity while reducing bandwidth consumption.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a job information cache as an intermediary component between external memory and the job processing units. This cache acts as a mediator that stores frequently accessed ancillary information locally, reducing direct accesses to external memory over the system bus. The intermediary cache resolves the bandwidth bottleneck while maintaining job processing throughput.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If the hardware accelerator lacks sufficient cache or memory for ancillary information, then the device complexity is reduced, but memory access latency increases

Engineering Contradiction:
Improvehardware accelerator memory structureVSAvoidmemory access latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent segments job information into distinct components: job-specific parameters and ancillary information. The ancillary information segment (cryptographic keys, initialization vectors, protocol information) is cached separately in a dedicated job information cache, while job-specific data flows through the main processing pipeline. This segmentation allows the system to maintain low device complexity while reducing memory access latency for the critical ancillary information.

Inventive Principle:
Principle #1Segmentation

3Reliability

If ancillary information size approaches the size of transmitted data, then data protection security is enhanced, but the quantity of data requiring memory access increases

Engineering Contradiction:
Improvedata protection securityVSAvoiddata volume requiring memory access
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts ancillary information (cryptographic keys, initialization vectors, protocol information) from the main data stream and stores it separately in a dedicated job information cache. This extraction allows the system to maintain enhanced data protection security through comprehensive ancillary information while reducing the quantity of data that requires repeated memory access during job processing.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8413153B2Methods and systems for sharing common job information
Publication Date: 2013.04.02 NXP USA INC
  • US8413153B2 patent drawing
  • US8413153B2 patent drawing
  • US8413153B2 patent drawing

AI summary

Apparatus and methods are provided for utilizing a plurality of processing units. A method comprises selecting a pending job from a plurality of unassigned jobs based on a plurality of assigned jobs for the plurality of processing units and assigning the pending job to a first processing unit. Each assigned job is associated with a respective processing unit, wherein the pending job is associated with a first segment of information that corresponds to a second segment of information for a first assigned job. The method further comprises obtaining the second segment of information that corresponds to the first segment of information from the respective processing unit associated with the first assigned job, resulting in an obtained segment of information and performing, by the first processing unit, the pending job based at least in part on the obtained segment of information.