Jogged Backside SRAM Bit Lines for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor feature sizes shrink, parasitic resistance and capacitance in SRAM devices increase, degrading the minimum operating voltage and speed, leading to sub-par performance and potential device failures.
Innovation Solution
The implementation of a new metal line routing scheme where bit lines and bit line bars are moved to the backside of the semiconductor device with jog offsets and partial landing on backside vias, increasing spacing between metal lines while maintaining sufficient metal volume, thereby reducing coupling capacitance without adversely affecting resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor feature sizes are shrunk to increase density, then storage capacity increases, but parasitic resistance and capacitance increase, degrading SRAM performance
Solution Approach 1:
The patent moves metal interconnects from the front side to the back side of the semiconductor device, utilizing the third dimension (depth/layer) to resolve the contradiction. By routing bit lines and word lines on the backside with jogged configurations, the design increases spacing between conductors to reduce parasitic capacitance while maintaining compact front-side transistor scaling for high density.
Solution Approach 2:
The metal interconnect system is segmented into front-side and back-side routing layers. The backside metal lines are further segmented into multiple segments with jogs (offsets) between adjacent lines, creating physical separation that reduces coupling capacitance while maintaining electrical connectivity through via structures.
2Area of stationary object
If metal lines are placed closer together to increase density, then area utilization improves, but coupling capacitance increases, reducing SRAM speed
Solution Approach 1:
The patent resolves the area-speed contradiction by utilizing the vertical dimension to separate metal lines onto different sides of the substrate. Backside metal lines with jogged configurations allow adequate spacing between adjacent bit lines and word lines, reducing coupling capacitance and improving switching speed while maintaining high area utilization through efficient routing topology.
Solution Approach 2:
The backside metal lines employ asymmetric jogged configurations where adjacent lines are offset relative to each other. This asymmetric arrangement maximizes spacing between lines of opposite polarity (bit line and bit line bar) to minimize capacitance, while maintaining compact overall footprint through strategic placement of the jogged segments.
3Speed
If metal line spacing is increased to reduce parasitic capacitance, then SRAM speed improves, but metal volume decreases, increasing resistance
Solution Approach 1:
The patent applies local quality by varying the cross-sectional dimensions of backside metal lines at different locations. Wider metal segments are used in regions where spacing requirements are less critical, while narrower segments with jogs are used where capacitance reduction is paramount. This localized dimension variation maintains sufficient metal volume and conductivity in critical regions while achieving capacitance reduction elsewhere.
Solution Approach 2:
The jogged metal line configuration creates a nested-like structure where wider metal portions are positioned to overlap or align with via structures, effectively nesting the via within or adjacent to the metal segment. This nesting approach maximizes the effective metal-via contact area, maintaining low resistance connections despite the reduced metal width in jogged regions.
Data Source
AI summary
A semiconductor device includes a first source/drain feature on a front side of a substrate. The device includes a first backside metal line under the first source/drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source/drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source/drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.