Joint Channel-Code Decoding Using Error Event Remainders
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Solution Overview
Problem
Existing joint channel-code detectors for linear block codes, particularly in magnetic recording channels, face performance degradation due to simplifying assumptions that limit error correction capability and increase complexity, leading to incorrect corrections and poor error detection in noisy channels.
Innovation Solution
A post processor architecture that generates a list of most likely error events, computes error event remainders, and determines error correction solutions using search logic, allowing for joint channel-code decoding with improved error correction capabilities and reduced complexity, enabling support for codes with large block lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If joint Maximum Likelihood channel-code detector is designed for linear block codes, then error correction capability is improved, but device complexity increases significantly
Solution Approach 1:
The joint channel-code detector is segmented into separate functional modules: a channel detector that processes received signals and a code decoder that performs error correction. This modular segmentation allows each component to be optimized independently, reducing overall system complexity while maintaining joint detection capabilities through structured interaction between modules.
Solution Approach 2:
The channel detector performs preliminary signal processing and error identification before the code decoder executes the main error correction algorithm. By pre-processing the received signal to identify likely error patterns and positions, the system reduces the computational burden on the subsequent decoding stage, thereby lowering device complexity while preserving reliability.
2Device complexity
If simplifying assumptions are made in post processor architecture, then device complexity is reduced, but measurement precision deteriorates due to incorrect error corrections
Solution Approach 1:
The post processor incorporates feedback mechanisms where error correction results are validated against the received signal and code constraints. If corrections lead to inconsistent states, the system iteratively refines the correction decisions. This feedback loop maintains measurement precision by detecting and correcting incorrect error corrections while keeping the architecture relatively simple through iterative refinement rather than complex parallel processing.
3Device complexity
If separate channel detector and code decoder are used, then device complexity is reduced, but reliability decreases due to performance degradation
Solution Approach 1:
The system merges the channel detection and code decoding functions into a coordinated joint processing architecture. Although implemented as separate modules for complexity management, the channel detector and code decoder are tightly coupled through shared data structures and iterative refinement processes, enabling them to function as an integrated system that achieves reliability comparable to fully joint detectors while maintaining modular simplicity.
4Reliability
If list of most likely error events is generated, then error correction capability is improved, but loss of time increases due to extensive searching
Solution Approach 1:
The system pre-generates and stores a list of most likely error events and their corresponding corrections before actual decoding occurs. This preliminary preparation allows the decoder to quickly reference and apply appropriate corrections without performing extensive real-time searches, thereby reducing processing time while maintaining high error correction capability through the pre-computed error event database.
Data Source
AI summary
Circuits, architectures, methods and algorithms for joint channel-code decoding of linear block codes, and more particularly, for identifying and correcting one or more errors in a code word and/or for encoding CRC (or parity) information. In one aspect, the invention focuses on use of (i) remainders, syndromes or other polynomials and (ii) Gaussian elimination to determine and correct errors. Although this approach may be suboptimal, the present error checking and/or detection scheme involves simpler computations and/or manipulations than conventional schemes, and is generally easier to implement logically. Since the complexity of parity-based error correction schemes increases disproportionately to the number of potential error events, the present invention meets a long-felt need for a scheme to manage error detection and/or correction in systems (such as magnetic recording applications) where there may be a relatively large number of likely error events, thereby advantageously improving reliability and/or performance in channel communications.