Joint Detection Accelerator for TD-SCDMA Signal Processing
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Solution Overview
Problem
Current joint detection systems in TD-SCDMA wireless communication face challenges in efficiently processing signals from multiple users, leading to interference and reduced performance, especially at low signal-to-noise ratios, due to the complexity of channel estimation and interference cancellation.
Innovation Solution
A joint detection accelerator is designed to perform joint detection of received signals using a programmable DSP and hardware circuitry, including a complex multiply accumulate unit, simplified complex multiply accumulate unit, and normalized floating point divider, which reduces memory accesses and power consumption while improving processing speed and precision through pre-scaling and pipelined architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If joint detection processing is performed using traditional software-based methods on a host processor, then flexibility and programmability are maintained, but processing speed and real-time performance deteriorate due to the computational complexity of channel estimation and interference cancellation
Solution Approach 1:
The patent replaces the software-based processing mechanism with a hardware-based joint detection accelerator. The accelerator uses dedicated hardware circuits including complex multiply-accumulate units, simplified complex multiply-accumulate units, and normalized floating-point dividers to perform joint detection operations in hardware rather than software, thereby achieving real-time processing of multiple user signals while maintaining the ability to handle computational complexity through parallel hardware operations
Solution Approach 2:
The joint detection accelerator is segmented into multiple specialized processing units: complex multiply-accumulate units for general computations, simplified complex multiply-accumulate units for specific operations where one complex value is restricted to ±1 or ±j, and normalized floating-point dividers. This segmentation allows each unit to be optimized for its specific function, improving overall processing speed while managing computational complexity through division of labor
2Measurement precision
If memory accesses are increased to store intermediate results during joint detection, then processing accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements different data path configurations with varying precision characteristics. The complex multiply-accumulate units and simplified complex multiply-accumulate units provide different levels of computational precision for different stages of processing. By using higher precision where needed and optimized precision where sufficient, the system maintains data extraction accuracy while reducing unnecessary power consumption from uniform high-precision operations throughout
Solution Approach 2:
The accelerator dynamically adjusts operational parameters including the use of simplified complex multiply-accumulate units for operations where one value is restricted to ±1 or ±j, and normalized floating-point dividers for division operations. These parameter changes optimize the balance between precision and power consumption by matching computational resources to the actual requirements of each processing stage
3Productivity
If chip operational modes are extended to reduce sleep duration, then processing throughput is improved, but power consumption increases
Solution Approach 1:
The joint detection accelerator is designed with dynamic power management capabilities that allow the chip to switch between active processing modes and low-power sleep modes. The hardware architecture supports rapid state transitions, enabling the system to maintain high processing throughput during active periods while efficiently entering sleep modes between processing tasks, thereby improving overall productivity without sustaining high power consumption continuously
Data Source
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AI summary
A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.