Joint Detection Decoding for Nonvolatile Memory Inter-Cell Interference
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Solution Overview
Problem
Current semiconductor memory systems face challenges in accurately detecting and decoding data from nonvolatile memory cells due to inter-cell interference and shifting threshold voltage distributions over time, leading to errors in data read operations.
Innovation Solution
The system employs a detector and decoder module that performs inter-cell interference cancellation, generates reliability indications based on adjacent cell states, and adjusts reference voltages to improve data decoding accuracy, using schemes such as Gray mapping and histogram-based calibration to mitigate errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional detection and decoding methods are used, then the system structure remains simple, but read errors increase due to inter-cell interference and voltage distribution shifts
Solution Approach 1:
The patent combines the detection and decoding functions into a unified joint detection and decoding system. The detector and decoder work together with shared components (reference voltage generation, threshold comparison) to simultaneously perform detection and decoding operations, reducing overall system complexity while improving reliability through coordinated operation.
Solution Approach 2:
The system implements feedback mechanisms where the detector provides reliability indications to the decoder, and the decoder uses this information to adjust its decoding process. The joint detection and decoding system uses feedback from threshold voltage measurements to dynamically adjust reference voltages and decoding thresholds, compensating for inter-cell interference and voltage distribution shifts.
2Measurement precision
If inter-cell interference cancellation is implemented, then data decoding accuracy improves, but processing complexity increases
Solution Approach 1:
The system performs preliminary actions by pre-calculating and storing threshold voltage distributions and interference characteristics in lookup tables. Before actual detection and decoding, the system pre-processes reference voltage values and threshold settings based on expected interference patterns, allowing the main detection algorithm to operate more simply while still achieving high accuracy through these pre-computed corrections.
Solution Approach 2:
The system changes parameters dynamically by adjusting reference voltages and detection thresholds based on detected interference levels. The detector monitors threshold voltage distributions and modifies operational parameters (reference voltage offsets, threshold values) to compensate for inter-cell interference, maintaining high measurement precision without requiring complex real-time calculations.
3Stability of the object's composition
If reference voltage adjustment is performed, then voltage distribution shifts are compensated, but additional processing steps are required
Solution Approach 1:
The system performs preliminary calibration of reference voltages during manufacturing or initial operation, storing optimized reference voltage values in lookup tables. This preliminary action captures the threshold voltage distribution characteristics, allowing the system to use pre-determined reference voltages during normal operation without requiring time-consuming real-time adjustments, thus maintaining stability while minimizing processing time.
Solution Approach 2:
The system implements periodic recalibration of reference voltages at scheduled intervals or after specific events (e.g., after erase operations or temperature changes). Instead of continuous adjustment, the reference voltages are updated periodically based on monitored threshold voltage distribution drift, maintaining compensation effectiveness while minimizing the time lost to adjustment operations.
Data Source
AI summary
A system including a receiving module to receive data from cells of memory, each cell storing multiple bits, each bit corresponding to a different type of page of the memory, the bits stored in a cell denoting a state of the cell, and the data including bits from a page of the memory or states of cells along a word line of the memory. A processor generates a reliability indication for a first portion of the data corresponding to a first cell based on the first portion of the data and one or more second portions of the data corresponding to one or more of the cells that are adjacent to the first cell. A decoder decodes the first portion of the data based on the first portion of the data and the reliability indication for the first portion of the data.