Joint Detector Accelerator Segmentation for TD-SCDMA
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Solution Overview
Problem
Current TD-SCDMA joint detection systems face challenges in reducing power consumption and increasing operation speed while maintaining high precision, particularly in channel estimation and interference cancellation, due to the need for large bit-widths and complex processing operations.
Innovation Solution
A joint detection system incorporating a joint detector accelerator (JDA) and a programmable digital signal processor (DSP) performs front-end and back-end processing, with pre-scaling of propagation channels and reduced bit-width implementations to enhance efficiency, allowing for flexible customization and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large bit-width implementations are used for joint detection processing, then measurement precision is improved, but use of energy increases and operation speed decreases
Solution Approach 1:
The joint detection system is segmented into two distinct processing stages: front-end processing performed by a joint detector accelerator (JDA) in hardware for high-speed low-power operation, and back-end processing performed by a programmable DSP for flexibility. This segmentation allows each component to be optimized for its specific function, resolving the contradiction between precision and power consumption.
Solution Approach 2:
The patent applies pre-scaling to propagation channels before joint detection processing, which transforms the channel parameters to reduce the required bit-width for accurate processing. By changing the parameter representation (scaling), the system achieves high detection precision with reduced bit-width implementations, thereby lowering power consumption while maintaining accuracy.
2Measurement precision
If large bit-width implementations are used for joint detection processing, then measurement precision is improved, but operation speed decreases
Solution Approach 1:
The processing is segmented such that the front-end processing requiring high precision is performed by the JDA hardware accelerator which operates at high speed with optimized fixed-point arithmetic, while the back-end processing handles the remaining computations. This segmentation enables high operation speed without sacrificing detection precision.
Solution Approach 2:
Pre-scaling of propagation channels transforms the data parameters to a format that requires smaller bit-widths for accurate processing. This parameter transformation enables the system to achieve high detection precision using reduced bit-width arithmetic operations, which execute faster and consume less computational resources.
3Measurement precision
If complex processing operations are performed for channel estimation and interference cancellation, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The complex joint detection algorithm is segmented into front-end processing (channel estimation and initial interference cancellation) performed by the dedicated JDA hardware, and back-end processing performed by the programmable DSP. This segmentation reduces device complexity by offloading computationally intensive operations to specialized hardware while maintaining precision.
Solution Approach 2:
The patent applies pre-scaling transformations to propagation channels and uses reduced bit-width representations for intermediate computations. These parameter changes simplify the processing operations required for channel estimation and interference cancellation, reducing device complexity while preserving measurement precision through careful management of numerical accuracy.
Data Source
AI summary
A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.