Josephson Parametric Amplifier Chip Fabrication With Laser Direct Writing
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Solution Overview
Problem
The complexity and inefficiency of preparing impedance matching Josephson parametric amplifiers due to the need for high processing accuracy and additional steps in electron beam exposure processes, such as exposure-coating-lifting off, which complicates the preparation process and reduces efficiency.
Innovation Solution
A chip preparation method using laser direct writing exposure to create underlying circuits and Josephson junctions, with a trial preparation process to determine oxidation conditions for precise oxide layer formation, simplifying the process and improving accuracy and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electron beam exposure processing process is used to prepare impedance matching Josephson parametric amplifier, then manufacturing precision is improved, but device complexity increases due to additional metal layer preparation and exposure-coating-lifting off process
Solution Approach 1:
The patent extracts and removes the additional metal layer preparation step from the electron beam exposure process. By using laser direct writing exposure instead of electron beam exposure, the method eliminates the need for overlay marks and the associated exposure-coating-lifting off process, thereby reducing process complexity while maintaining manufacturing precision through direct laser patterning of the photoresist layer
Solution Approach 2:
The patent replaces the electron beam exposure system with a laser direct writing exposure system. This substitution eliminates the need for complex metal layer preparation and overlay mark processes, simplifying the overall fabrication process while maintaining the ability to achieve high processing accuracy for Josephson junctions
2Manufacturing precision
If electron beam exposure processing process is used to prepare impedance matching Josephson parametric amplifier, then manufacturing precision is improved, but productivity decreases due to additional exposure-coating-lifting off process
Solution Approach 1:
The patent extracts and eliminates the time-consuming exposure-coating-lifting off process steps from the fabrication sequence. By using laser direct writing exposure, the method directly patterns the photoresist layer without requiring additional metal layer preparation, overlay mark creation, or lifting off steps, thereby significantly reducing total process time and improving preparation efficiency
Solution Approach 2:
The patent replaces the multi-step electron beam exposure process with a single-step laser direct writing exposure process. This substitution eliminates the need for additional coating and lifting off steps, reducing the total number of process steps and improving productivity while maintaining the precision required for Josephson junction fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures accurate preparation of Josephson junctions and impedance Josephson parametric amplifiers by simplifying the process, reducing complexity, and increasing preparation efficiency while maintaining high accuracy.
Implementation Method 1
preparing, on a substrate by using a laser direct writing exposure manner, a first underlying circuit of an impedance Josephson parametric amplifier
Implementation Method 2
determine an oxidation condition for preparing an oxide layer in the Josephson junction
Data Source
AI summary
A chip preparation method and system, and a chip are provided. The method includes: preparing, by using a laser direct writing exposure manner, a first underlying circuit of an impedance Josephson parametric amplifier and a second underlying circuit for testing, to obtain a first chip product; generating, on the first chip product by using the laser direct writing exposure manner, a photoresist structure for preparing a Josephson junction; cutting, from the first chip product, a second chip product on which the second underlying circuit is located and a third chip product on which the first underlying circuit is located; preparing a Josephson junction sample based on a photoresist structure corresponding to the second underlying circuit, to obtain an oxidation condition; and preparing, according to the oxidation condition, the Josephson junction based on a photoresist structure corresponding to the first underlying circuit.