Josephson Junction Fabrication via Dual Damascene Process
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Solution Overview
Problem
Current methods for fabricating superconducting devices, such as Josephson junctions, face challenges in mass production due to the need for low temperature processing and the use of aggressive chemistries, which result in large device sizes, low yield, and reliability issues, limiting the density and functionality of integrated chips.
Innovation Solution
A scalable method integrating a niobium-based Josephson junction into a dual damascene process with a hardmask etch and in-situ sidewall passivation, eliminating the need for aggressive chemical cleaning and anodization, and allowing for smaller junction sizes and higher density interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-aligned anodization process is used to form Josephson junction, then insulation between active part and top electrode wiring is achieved, but JJ area becomes relatively large due to masking and etching requirements
Solution Approach 1:
The patent extracts and removes the blanket anodization layer from areas surrounding the JJ ring using selective etching, eliminating the need for large masking areas while maintaining insulation where needed
Solution Approach 2:
The anodization layer is selectively removed only from specific regions around the JJ ring while being retained in other areas, creating local variations in insulation properties that reduce overall JJ area without compromising reliability
2Ease of manufacture
If legacy processing techniques are used to form Josephson junction, then device fabrication is achieved, but large topography problems occur resulting in low yield and reliability
Solution Approach 1:
The patent performs preliminary planarization by depositing and polishing a planarization layer before forming the JJ structure, ensuring a flat surface that eliminates topography problems in subsequent processing steps
Solution Approach 2:
A planarization layer is introduced as an intermediary between the substrate and the JJ structure, absorbing topography variations and providing a uniform surface for precise device fabrication
3Reliability
If thick passivation layer is formed around JJ ring, then insulation is provided, but minimum JJ size is limited to order of 1 um diameter
Solution Approach 1:
The patent changes the parameters of the anodization layer by selectively removing it from certain regions, transforming it from a continuous thick layer to a patterned structure that provides insulation only where necessary, thereby reducing the minimum JJ size
Solution Approach 2:
The continuous anodization layer is segmented into discrete regions that provide insulation only where needed around the JJ ring, eliminating unnecessary material and reducing the overall device footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances yield and uniformity, supports scaling into very large scale superconducting electronics, and increases junction density by eliminating the need for extra insulating layers and aggressive chemistries, enabling more efficient and reliable fabrication of high-density multilevel interconnects.
Implementation Method 1
etching away a portion of the junction material stack to form a Josephson junction
Implementation Method 2
depositing a second dielectric layer over the hardmask, the JJ, the base electrode and the first dielectric layer
Implementation Method 3
a self-aligned anodization process which uses a highly corrosive electrochemical bath to form a protective thick passivation layer around the JJ
Data Source
Figure 1~2
Figure 3~4
Figure 5~7
AI summary
The disclosed method of forming a Josephson junction (JJ) based superconductor device structure comprises forming a base electrode (18) in a first dielectric layer (16) with coplanar surfaces, preferably by a damascene process, forming a junction material stack over the base electrode, forming a hardmask (34) over the junction material stack, etching away a portion of the junction material stack to form the JJ (24), depositing a second dielectric layer (22), and forming a first contact (26) through the second dielectric layer to the base electrode and a second contact (28) through the second dielectric layer and the hardmask, preferably by a dual damascene process.