Josephson Junction Interconnect Structure Planarization
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Solution Overview
Problem
Current methods for fabricating superconducting devices, such as Josephson junctions, face challenges in mass production due to the need for low-temperature processing and legacy techniques that result in large topography issues, limiting the density and functionality of integrated chips.
Innovation Solution
A scalable Josephson junction process integrated into a planarized superconducting interconnect using a dual damascene formation with a niobium-based JJ and a counter-electrode extending to a dielectric surface, eliminating the need for extra insulating layers and allowing for high-density multilevel interconnects by using smaller contacts and conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-aligned anodization process is used to form Josephson junctions, then insulation between active JJ and top electrode wiring is achieved, but JJ area becomes relatively large due to masking and etching requirements
Solution Approach 1:
The patent extracts the insulating function from the anodization process by using a separate dielectric layer (e.g., SiO2, Si3N4) deposited over the base electrode. This dielectric layer provides the necessary insulation between the JJ and top electrode wiring without requiring the anodization step, thereby reducing the JJ area while maintaining electrical isolation.
Solution Approach 2:
The patent segments the insulating function into a dedicated dielectric layer rather than relying on the anodization layer. This allows the JJ structure to be minimized in area while the insulation requirement is satisfied by the separate dielectric layer, resolving the contradiction between small JJ area and reliable insulation.
2Ease of manufacture
If legacy processing techniques are used to form Josephson junctions, then Josephson junctions can be manufactured, but large topography problems occur resulting in yield and reliability issues
Solution Approach 1:
The patent performs preliminary planarization by depositing a dielectric layer over the base electrode before forming the JJ structure. This creates a flat surface that eliminates topography problems subsequent to the JJ formation, ensuring uniformity and improving yield while maintaining ease of manufacture.
Solution Approach 2:
The dielectric layer serves as an intermediary between the base electrode and subsequent JJ layers. It provides a planarized surface that mediates the topography issues, allowing legacy processing techniques to be used while achieving uniform JJ formation and improving manufacturing precision.
3Reliability
If anodization process is used to form Josephson junctions, then insulation is provided, but minimum JJ size is limited to order of 1um diameter which limits density and functionality
Solution Approach 1:
The patent extracts the insulation function from the anodization process and assigns it to a separate dielectric layer. This allows the JJ size to be minimized for high density integration while the dielectric layer provides the necessary insulation, thereby improving productivity through increased JJ density and chip functionality.
Solution Approach 2:
The patent moves the insulation function to a different dimensional layer by using a dedicated dielectric layer deposited over the base electrode. This separates the insulation requirement from the JJ planar dimensions, allowing JJ size to be reduced in the plane while insulation is maintained in the vertical dimension, thus improving density and productivity.
4Productivity
If dual damascene formation with planarized surface is used, then high-density multilevel interconnects are enabled, but additional processing steps are required compared to legacy techniques
Solution Approach 1:
The patent merges the planarization function into the dielectric layer deposition step by using conformal deposition techniques. This combines the insulation provision and surface planarization into a single processing step, enabling high-density multilevel interconnects while minimizing the increase in device complexity.
Solution Approach 2:
The dielectric layer is designed to serve multiple functions: providing insulation between JJ and top electrode, planarizing the surface for subsequent interconnect formation, and serving as a base for multilevel interconnect structures. This multi-functionality enables high-density integration without proportionally increasing processing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-density superconducting interconnects with increased Josephson junction density and improved reliability, facilitating the mass production of superconducting devices by overcoming the limitations of legacy processing techniques.
Implementation Method 1
Superconducting circuits are one of the leading technologies proposed for quantum computing and cryptography applications
Implementation Method 2
One of the common devices employed in superconducting circuits is a Josephson junction (JJ)
Data Source
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AI summary
A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a base electrode in the first dielectric layer with the base electrode having a top surface aligned with the top surface of the first dielectric layer. The method further comprises forming a Josephson junction (JJ) over the base electrode, depositing a second dielectric layer over the JJ, the base electrode and the first dielectric layer, and forming a first contact through the second dielectric layer to the base electrode to electrically couple the first contact to a first end of the JJ, and a second contact through the second dielectric layer to a second end of the JJ.