JPEG Accelerator Memory Layout for Data Processing
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Solution Overview
Problem
General-purpose processors in data centers are inefficient for high-capacity network and storage workloads due to their poor performance in processing packet streams.
Innovation Solution
A highly programmable data processing unit (DPU) with specialized hardware-based accelerators, such as a JPEG accelerator, offloads tasks by performing acceleration functions for data processing, including parallel coding and decoding of image data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose processors are used for packet stream processing, then device versatility is maintained, but processing speed and productivity deteriorate
Solution Approach 1:
The processor is segmented into multiple processing cores, each capable of independently processing different packets or packet streams simultaneously. This parallel architecture maintains versatility while dramatically improving throughput by dividing the workload across multiple execution units rather than relying on a single general-purpose core.
Solution Approach 2:
The processing system employs dynamic resource allocation where processing cores can be adaptively assigned to different packet types, protocols, or processing tasks based on real-time workload characteristics. This dynamic flexibility allows the system to maintain versatility across different applications while optimizing processing speed for current demands.
2Manufacturing precision
If context-based coding is performed sequentially for image blocks, then coding accuracy is improved, but processing time increases
Solution Approach 1:
The system performs preliminary actions by pre-calculating and storing context information from previously processed blocks in a buffer or cache. When processing subsequent blocks, this pre-prepared context data is readily available, allowing parallel processing units to perform context-based coding without waiting for sequential completion of all preceding blocks, thus reducing processing time while maintaining accuracy.
Solution Approach 2:
The patent transitions from a single-dimensional sequential processing approach to a multi-dimensional parallel processing architecture. Multiple processing elements operate simultaneously on different image blocks, each utilizing context information from their respective spatial or temporal neighborhoods. This dimensional expansion allows context-based coding accuracy to be maintained across multiple parallel streams rather than being constrained to a single sequential path.
Data Source
AI summary
A device includes a memory configured to store image data and an image coding unit implemented in circuitry. The image coding unit is configured to store a first portion of a set of context information in memory of the image coding unit as an array representing a direct access table and store a second portion of the set of context information in a hash table. The image coding unit is further configured to determine whether a context value for context-based coding of a value of an instance of a syntax element for a block of image data is stored in the array or in the hash table, retrieve the context value from either the array or the hash table according to the determination, and context-based code the value of the instance of the syntax element using the context value.