JTAG-Based Secure BIOS Integrity Mechanism
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Solution Overview
Problem
Existing methods for securing a computing system's BIOS struggle to balance accessibility for upgrades with protection against unauthorized tampering, as moving BIOS storage onto the microprocessor's die complicates upgrades, while encryption methods degrade system performance.
Innovation Solution
A system that includes a BIOS ROM with plaintext contents and an encrypted message digest, a tamper detector, a random number generator, and a JTAG control chain to periodically check and validate the BIOS integrity during system operation, preventing operation if tampering is detected, without the need for costly on-die memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BIOS storage is moved onto the microprocessor's die to protect against tampering, then security against unauthorized access is improved, but ease of upgrade deteriorates
Solution Approach 1:
The BIOS storage is segmented into two parts: the critical integrity verification data (message digest) is placed on the microprocessor die for security, while the main BIOS storage remains separate and upgradable. This segmentation allows security-critical elements to be protected on-die while keeping the bulk of BIOS content accessible for easy upgrades.
Solution Approach 2:
An encrypted message digest acts as an intermediary between the BIOS contents and the security verification mechanism. The message digest is stored in plaintext on-die for quick verification, while the full BIOS remains off-die for easy upgrading. The encrypted nature of the message digest provides security without requiring the full BIOS to be encrypted or on-die.
2Reliability
If encryption is applied to BIOS contents to protect against tampering, then security against unauthorized access is improved, but system performance deteriorates
Solution Approach 1:
The security verification function is extracted from the main BIOS execution path. Instead of encrypting the entire BIOS and requiring decryption during every operation, only a small message digest is encrypted and verified periodically. This extraction eliminates the performance overhead of continuous decryption while maintaining security through periodic verification.
Solution Approach 2:
Instead of applying encryption to the entire BIOS content (excessive action), the patent applies encryption only to a small message digest (partial action). This partial encryption provides sufficient security verification without the performance penalty of encrypting and decrypting large amounts of data during system operation.
Data Source
AI summary
An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, and a JTAG control chain. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest, where the encrypted message digest has an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is operatively coupled to the BIOS ROM, and is configured to generate a BIOS check interrupt at a combination of prescribed intervals and event occurrences, and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest, and is configured to compare the second message digest with the decrypted message digest, and is configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal, where the event occurrences include input/output accesses. The random number generator disposed within the microprocessor, and generates a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied. The JTAG control chain is configured to program the combination of prescribed intervals and event occurrences within tamper detection microcode storage.