JTAG Clock Synchronization for Variable IC Speeds
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Solution Overview
Problem
Testing complex surface mount devices and printed circuit boards with high IC density and varied internal clock speeds requires reconfiguration of test fixtures, leading to increased complexity and cost, as existing non-contact methods struggle to synchronize JTAG and internal clocks effectively.
Innovation Solution
A synchronization subsystem that monitors transitions of the test interface clock and internal clock to synchronize JTAG and embedded device clocks, allowing for efficient down-conversion of JTAG clocks to integer fractions of the internal clock, enabling testing of devices with different internal clock speeds without reconfiguring the test fixture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If test fixtures are reconfigured to test devices with different internal clock speeds, then testing capability is improved, but device complexity and cost increase
Solution Approach 1:
The test fixture is designed with a universal clock synchronization subsystem that can adapt to devices with different internal clock speeds without requiring physical reconfiguration. The system measures the internal clock frequency and dynamically synchronizes the JTAG clock accordingly, allowing a single fixture to test multiple device types with varied clock characteristics.
Solution Approach 2:
The test fixture employs dynamic clock synchronization where the JTAG clock frequency is automatically adjusted based on real-time measurement of the device's internal clock speed. This dynamic adaptation eliminates the need for static reconfiguration and enables the fixture to handle various clock speeds seamlessly.
2Adaptability or versatility
If probe tips are reduced or contact apparatus are altered to test higher pin pitches, then testing capability is improved, but device complexity and cost increase
Solution Approach 1:
The invention replaces mechanical reconfiguration approaches with an electronic/software-based clock synchronization system. Instead of physically altering probe tips or contact apparatus, the system uses automated frequency measurement and clock domain synchronization to achieve compatibility with different pin pitches and device configurations.
3Measurement precision
If clock domains are synchronized between TCK and internal clock, then data transfer accuracy is improved, but synchronization complexity increases
Solution Approach 1:
The system implements self-service clock synchronization by automatically measuring the device's internal clock frequency and configuring the JTAG clock accordingly. The synchronization process is autonomous, requiring no manual intervention or complex external control logic, thereby simplifying the overall system while maintaining high data transfer accuracy.
Solution Approach 2:
The clock synchronization mechanism uses feedback from internal clock frequency measurements to dynamically adjust the JTAG clock settings. The system continuously monitors and adapts the clock domains based on measured parameters, ensuring accurate data transfer while keeping synchronization logic manageable through closed-loop control.
Data Source
AI summary
A system and methods to transfer data between a testing interface and an IC. The system may include a synchronization subsystem to monitor the transitions of the test interface clock and/or IC clock to determine a clock adjustment appropriate to substantially synchronize the clocks. In certain implementations, a synchronization unit on an IC under test counts a predetermined number of transitions of an internal clock of an embedded device and generates a signal upon reaching a terminal count, which signal is received by a host controller associated with a JTAG test fixture. In such implementations, the host controller determines the number of IC clock cycles that occurred during the predetermined number of IC clock cycles and synthesizes a synchronized JTAG clock that is a integral fraction of the IC clock.