JTAG Cell Addressing for Flash Memory Direct Access
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Solution Overview
Problem
Current non-volatile memory technologies in System-on-Chip (SoC) devices face challenges with integration complexity, increased programming space requirements, and difficulty in managing embedded memory, especially at lithography nodes below 28 nm, leading to high latency and power consumption issues.
Innovation Solution
A structurally independent flash memory component is introduced, utilizing a modified JTAG cell addressing system for direct memory access, which includes a memory array, micro-sequencer, control logic, sense amplifiers, and optimized read Finite State Machine, allowing for high-frequency data access and reducing latency through a scalable architecture with enlarged memory pages and Error Correction Codes (ECC) integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional embedded flash memory is used in SoC devices, then storage capacity is provided, but integration complexity increases and management becomes difficult at lithography nodes below 28 nm
Solution Approach 1:
The memory system is segmented into distinct functional blocks including a memory array, sense amplifiers, JTAG cells, and a controller. Each block operates independently with defined interfaces, allowing modular integration into SoC devices while reducing overall system complexity.
Solution Approach 2:
A controller acts as an intermediary between the host device and the memory component, managing complex operations such as read, write, and erase cycles. The controller translates high-level commands into low-level memory operations, simplifying the interface for system designers.
2Productivity
If traditional memory access methods are used, then data can be retrieved, but latency is high and throughput is limited
Solution Approach 1:
The system performs preliminary actions by pre-charging sense amplifiers and pre-positioning data in buffers before actual read operations are required. This reduces the time needed for data retrieval by preparing the memory subsystem in advance.
Solution Approach 2:
The memory system maintains continuous operation by overlapping read, write, and erase operations across different memory blocks. While one block is being read, another can be written to or erased, ensuring continuous productive activity without idle cycles.
3Quantity of substance
If larger memory arrays are integrated, then storage capacity increases, but power consumption increases
Solution Approach 1:
The memory system implements local quality by enabling only the specific memory blocks and sense amplifiers needed for each operation. Instead of activating the entire memory array, only the relevant local sections are powered and operated, reducing overall power consumption while maintaining large storage capacity.
Solution Approach 2:
The memory controller uses periodic action by organizing memory operations into structured sequences with idle periods between intensive operations. Write and erase operations, which consume significant power, are spaced out and interleaved with lower-power read operations, allowing power management and thermal dissipation.
Data Source
AI summary
The present disclosure relates to a Flash memory component having a structurally independent structure and coupled to a System-on-Chip through a plurality of interconnection pads, comprising:a memory array including a plurality of independently addressable sub arrays;sense amplifiers coupled to corresponding outputs of said sub arrays and coupled to a communication channel of said System-on-Chip;a scan-chain comprising modified JTAG cells coupled in parallel between the output of the sense amplifiers and said communication channel to allow performing read operations in a Direct Memory Access.