JTAG-Addressed Flash DMA for Low-Latency SoC Memory Reads
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Solution Overview
Problem
Current non-volatile memory technologies in System-on-Chip (SoC) devices face challenges with embedded flash memory integration, particularly in reducing latency and improving throughput, especially as lithography nodes decrease below 28 nm, and existing direct memory access systems are inefficient in managing large memory arrays.
Innovation Solution
A structurally independent flash memory component is integrated with SoC devices using a modified JTAG cell addressing system and Direct Memory Access (DMA) configuration, which includes optimized read operations and error correction mechanisms, allowing for larger memory integration with reduced latency and increased throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If embedded flash memory is integrated in SoC devices, then storage capacity increases, but initial latency increases and throughput decreases
Solution Approach 1:
The memory array is divided into multiple sub-arrays, each with its own sense amplifier and JTAG cell interface. This segmentation allows parallel access to different memory regions, reducing initial latency while maintaining large storage capacity. The controller can independently address and access multiple sub-arrays simultaneously.
Solution Approach 2:
The patent introduces a new interface architecture that adds a dimensional layer between the controller and memory array. The JTAG cell-based addressing system creates an additional addressing dimension that enables direct access to memory cells without traditional row-column decoding delays, thereby reducing initial latency.
2Quantity of substance
If embedded flash memory is integrated in SoC devices, then storage capacity increases, but throughput decreases
Solution Approach 1:
The memory system is segmented into multiple independent sub-arrays that can be accessed in parallel. Each sub-array has dedicated sense amplifiers and JTAG cells, enabling simultaneous read/write operations across multiple memory regions, thereby increasing overall throughput while maintaining large storage capacity.
Solution Approach 2:
The patent implements a continuous data transfer mechanism where the JTAG cell interface maintains uninterrupted data flow between the controller and memory array. The boundary scan capability allows continuous verification and transfer of data bits through the scan chain, eliminating idle cycles and improving throughput.
3Device complexity
If traditional memory addressing is used, then system complexity is low, but access speed is slow
Solution Approach 1:
The JTAG cell acts as an intermediary between the traditional addressing system and the memory array. Instead of using complex row-column decoders, the patent uses JTAG boundary scan cells to directly address and access memory locations. This intermediary approach simplifies the addressing logic while significantly improving access speed through direct cell targeting.
4Quantity of substance
If larger memory arrays are integrated, then storage capacity increases, but power consumption increases
Solution Approach 1:
The large memory array is divided into smaller sub-arrays that can be independently accessed. This segmentation allows the system to activate only the necessary sense amplifiers and JTAG cells for each access operation, reducing overall power consumption while maintaining large storage capacity. inactive sub-arrays remain in low-power state.
Data Source
AI summary
The present disclosure relates to a Flash memory component having a structurally independent structure and coupled to a System-on-Chip through a plurality of interconnection pads, comprising:a memory array including a plurality of independently addressable sub arrays;sense amplifiers coupled to corresponding outputs of said sub arrays and coupled to a communication channel of said System-on-Chip;a scan-chain comprising modified JTAG cells coupled in parallel between the output of the sense amplifiers and said communication channel to allow performing read operations in a Direct Memory Access.A method for retrieving data from the memory component is also disclosed.