JTAG Memory Access Controller Sequential Block Read
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Solution Overview
Problem
The increasing complexity and density of surface mount technology on printed circuit boards, particularly with devices having minimal pin spacing, lead to costly and complex contact test methods, and the need for substantial modifications to test fixtures for testing ICs on both sides of the board.
Innovation Solution
The implementation of a JTAG-based system that allows for sequential data memory access through a serial access port, enabling a JTAG test device to send a single memory access command for read or write operations, allowing other test protocols to execute concurrently and reducing the total test time by using a memory access controller that increments addresses automatically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact test methods are used for high-density ICs with minimal pin spacing, then testing capability is achieved, but test fixture complexity and cost increase substantially
Solution Approach 1:
The patent replaces mechanical contact-based testing with non-contact electromagnetic field-based testing. The test fixture uses electromagnetic fields to interact with boundary scan cells within the IC, eliminating the need for physical probes to contact pins. This substitution resolves the contradiction by maintaining testing capability while dramatically reducing fixture complexity and cost.
Solution Approach 2:
The patent introduces boundary scan cells as intermediary elements embedded within the IC. These cells serve as mediators between the non-contact test fixture and the internal circuitry, enabling indirect observation and control of signal states without direct physical contact. This intermediary approach allows testing of high-density ICs without requiring complex contact-based fixtures.
2Ease of operation
If conventional TAP control is used for memory access, then serial communication is maintained, but multiple individual commands are required increasing test time
Solution Approach 1:
The patent merges multiple individual memory access commands into a single block access command. Instead of sending separate TDI/TDO sequences for each memory address, the system transmits a unified command that specifies a starting address and block size, causing the memory access controller to automatically sequence through multiple addresses. This merging maintains serial communication simplicity while dramatically reducing the number of communication cycles required.
Solution Approach 2:
The patent implements preliminary action by having the memory access controller pre-configure automatic address incrementing and block access sequencing before actual data transfer begins. The controller receives preliminary parameters (start address, block size) and automatically generates the sequence of memory access operations without requiring intermediate host intervention for each address, thereby reducing test time while maintaining serial communication.
3Ease of operation
If sequential memory access is implemented through TAP, then memory read/write operations are enabled, but each access requires separate command sequences reducing productivity
Solution Approach 1:
The patent implements self-service by enabling the memory access controller to automatically manage sequential memory addressing and data transfer without continuous host intervention. Once a block access command is received, the controller autonomously increments addresses, manages read/write operations, and sequences data transfer through the TAP interface. This self-service capability maintains ease of operation while dramatically improving productivity by eliminating repetitive command sequences.
Solution Approach 2:
The patent ensures continuity of useful action by implementing automatic block access sequencing that continuously transfers multiple memory words through the TAP interface without interruption. The memory access controller maintains continuous data flow by automatically advancing to the next address in the sequence, keeping the serial communication channel continuously productive rather than idle between individual access operations.
Data Source
AI summary
A system and method for executing a sequential data memory access through a serial access port is provided. The system may include a memory access controller to receive a block access command and successively access data elements in the block. In certain implementations, a test device, such as a JTAG host, transmits a block read or write command specifying a start address and an increment value to an embedded device under test, whereupon a memory access controller in the embedded device sequentially accesses the data at the start address, increments the address by the increment value, accesses the data at the incremented address, and repeats this procedure to sequentially access each of the remaining data elements in the block.