JTAG Packetization for Latency Reduction

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Solution Overview

Problem

Existing JTAG communication systems face latency issues due to high latency and low bandwidth connections, especially over long distances, which hinder efficient debugging and fault isolation processes.

Innovation Solution

Incorporating JTAG interface circuitry within the target system to perform higher-level operations such as polling and read-modify-write operations, reducing the need for frequent communication with debug tooling by optimizing data transmission and locally executing operations within the target system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If JTAG communication is performed over long-distance connections, then device accessibility is improved, but latency increases and bandwidth decreases

Engineering Contradiction:

Improvedevice accessibilityVSAvoidlatency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by performing operations locally within the target system before they would need to be communicated to debug tooling. The JTAG interface circuitry executes polling operations, read-modify-write operations, and other debug functions directly at the target system, eliminating the need to wait for remote debug tooling instructions and responses. This preliminary local execution significantly reduces latency while maintaining long-distance accessibility.

Inventive Principle:

Principle #10Preliminary action

2Ease of operation

If JTAG operations are performed remotely via debug tooling, then operational control is improved, but communication overhead increases

Engineering Contradiction:

Improveoperational controlVSAvoiddata transmission

Core Design Contradiction:

Ease of operationVSQuantity of substance

Solution Approach 1:

The patent extracts higher-level operational logic from the remote debug tooling and places it directly into the JTAG interface circuitry of the target system. By taking out the intelligence for performing polling, read-modify-write operations, and other complex JTAG functions from the external debug tooling, the system eliminates excessive data transmission and communication overhead while maintaining operational control through the remaining essential communications.

Inventive Principle:

Principle #2Taking out (Extraction)

3Adaptability or versatility

If traditional JTAG communication protocols are used, then compatibility is improved, but efficiency deteriorates due to high latency

Engineering Contradiction:

Improveprotocol compatibilityVSAvoidoperation efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces a new dimension of operation by implementing local execution capability within the target system's JTAG interface circuitry. This dimensional shift from purely remote command-execution to hybrid local-execution-with-remote-supervision creates a three-dimensional operational model that maintains protocol compatibility while dramatically improving efficiency by eliminating round-trip communication delays for routine operations.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11199586B2JTAG scans through packetization

Publication Date: 2021.12.14 INTEL CORP

AI summary

A Joint Test Access Group (JTAG) device can include a Joint Test Access Group (JTAG) port, transport layer circuitry to provide a communication to and from a debug device, and packet interpreter circuitry communicatively coupled between the JTAG port and the transport layer circuitry, the packet interpreter circuitry to translate data in a packet from the debug device into a sequence of bits to be provided to the JTAG port.