JTAG Registers with Concurrent Inputs for Flash Memory
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Solution Overview
Problem
Current non-volatile Flash memory technologies face challenges in managing data parallelism and storage space efficiency, especially as lithography nodes approach 28 nm, leading to increased demand for on-board memory that exceeds physical limits and complicates integration in System-on-Chip (SoC) devices.
Innovation Solution
A non-volatile memory device architecture that includes an array of Flash memory cells organized in sub-arrays with associated decoding and sensing circuitry, utilizing a JTAG interface and boundary-scan architecture to optimize communication with SoC devices, reducing latency and increasing throughput by allowing direct memory access and flexible data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional eFlash components are used in SoC devices, then integration is achieved, but storage space is limited by physical constraints at lithography nodes below 28 nm
Solution Approach 1:
The memory system is divided into multiple independently addressable memory banks (e.g., BANK0, BANK1, BANK2, BANK3) that can be accessed simultaneously through parallel JTAG interfaces. Each bank operates independently with its own address and data registers, enabling multi-core operation and increasing total storage capacity without proportionally increasing chip area.
Solution Approach 2:
The patent transitions from single-bit serial JTAG access to multi-bit parallel access by introducing multiple data registers (DATA0, DATA1, DATA2, DATA3) that can transfer data simultaneously. This dimensional expansion from 1-bit to N-bit parallelism dramatically increases throughput and effective storage access capacity without linearly increasing physical interface area.
2Productivity
If traditional JTAG interface is used, then simple architecture is maintained, but data transfer speed and throughput are limited
Solution Approach 1:
Multiple data registers (DATA0, DATA1, DATA2, DATA3) and address registers are merged into a unified JTAG interface architecture that shares common control logic and state machine. This consolidation enables parallel data paths while maintaining a single standardized JTAG interface, increasing throughput without proportionally increasing interface complexity.
Solution Approach 2:
The JTAG interface is enhanced to serve multiple functions simultaneously: it supports traditional single-bit serial access, multi-bit parallel data transfer, independent bank selection, and concurrent access by multiple cores. The same interface infrastructure handles both legacy JTAG operations and high-speed parallel memory access, eliminating the need for separate dedicated interfaces.
3Adaptability or versatility
If single-core access architecture is used, then simple control logic is maintained, but multi-core operation and data parallelism cannot be achieved
Solution Approach 1:
The memory system is divided into multiple independently addressable memory banks (e.g., BANK0, BANK1, BANK2, BANK3) that can be accessed simultaneously through parallel JTAG interfaces. Each bank operates independently with its own address and data registers, enabling multi-core operation and increasing total storage capacity without proportionally increasing chip area.
Solution Approach 2:
The control logic dynamically selects which data register and memory bank to access based on the current JTAG operation mode. The system can switch between single-bit serial mode, multi-bit parallel mode, and different bank selections without hardware reconfiguration, adapting to the needs of single-core or multi-core operations seamlessly.
4Loss of time
If serial JTAG access is used, then low area overhead is maintained, but initial latency in first access is high
Solution Approach 1:
Address registers and data registers are pre-configured and held ready in the JTAG interface logic, allowing the first memory access to proceed immediately without requiring sequential bit-by-bit address construction. The parallel data paths are pre-established, enabling rapid data transfer as soon as the memory operation is initiated, significantly reducing initial access latency.
Data Source
AI summary
The present disclosure relates to an apparatus comprising a host device and a memory component coupled to the host device. The memory component can comprise an array of memory cells, and an interface comprising a boundary scan architecture, wherein the boundary scan architecture includes an instruction register configured to store data indicative of a presence of a test data input (TDI) signal.