JTAG Scan Length Storage Unit for Variable Signal Groups
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Solution Overview
Problem
The efficiency of test and debug operations on digital signal processors is limited by the need for frequent loading of scan length registers in scan control units, especially at high test clock speeds, leading to high bus bandwidth consumption and reduced time for loading control information and executing instructions.
Innovation Solution
A storage unit with multiple scan length registers of varying lengths is provided, allowing a single command from the test and debug unit to identify and transfer the appropriate register contents to the target processor without additional communication, enabling efficient transfer of variable-length signal groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the scan length register is loaded before each scan operation, then the scan control unit can accommodate different scan path lengths, but the number of register loading operations increases, reducing testing efficiency
Solution Approach 1:
The patent pre-loads multiple scan length values into a scan length register array before testing begins. During operation, the appropriate scan length is selected by a counter value rather than requiring dynamic reloading. This preliminary preparation eliminates repeated register loading operations during the testing process, resolving the contradiction between adaptability to different scan lengths and testing efficiency.
2Speed
If the test clock speed is increased to improve testing speed, then more bits can be scanned per unit time, but the frequency of register loading operations increases, consuming more bus bandwidth
Solution Approach 1:
By pre-loading all necessary scan length values into the register array before high-speed testing begins, the system enables sustained high test clock speeds without frequent bus transactions. The counter-based selection mechanism operates locally without requiring continuous bus access, thereby reducing bus bandwidth consumption while maintaining high testing speed.
Solution Approach 2:
The patent divides the scan length register into multiple segments or entries in an array, each storing a different scan length value. This segmentation allows the system to store multiple configuration values simultaneously, eliminating the need for sequential reloading during operation and reducing bus bandwidth consumption during high-speed testing.
3Productivity
If the data path between test and debug unit and scan control unit is widened to improve data transfer efficiency, then more data can be transferred simultaneously, but additional pins are required on the scan control unit device
Solution Approach 1:
The patent segments the scan length register into multiple smaller registers arranged in an array. Each register stores a portion of the scan length information, allowing the system to achieve the functionality of a wide data path using multiple smaller, manageable registers. This approach improves data transfer efficiency without requiring a single wide data path that would demand additional pins.
Data Source
AI summary
In a JTAG test and debug environment, the signal groups for boundary scans can have several lengths including signal groups that are longer that the shift register out. A storage unit is provided with a plurality of storage location lengths. The boundary scan signal groups are stored in a location having a suitable storage capacity. The command that transfers the boundary scan signal group includes a parameter identifying the relevant location. The scan control unit, upon receiving the command, transfers the entire boundary scan signal group as a result this command even if several transfers through the shift register out are required.