JTAG Scan Circuit Using Local Clock Buffers
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Solution Overview
Problem
Current JTAG scanning methods are limited by the external JTAG clock speed, leading to slow scan speeds and complex clock tree distribution, which restricts the operational speed and complexity of internal operations, especially in large integrated circuits.
Innovation Solution
A faster internal clock signal is introduced for the scan chain, generated by oversampling the external JTAG clock, allowing multiple internal scan operations to complete within a single external JTAG cycle, and using a clock mesh with local clock buffers to distribute the signal efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the external JTAG clock speed is used to drive the scan chain, then the scan operations can be performed externally, but the scan speed is limited and the clock tree distribution becomes complex
Solution Approach 1:
The patent divides the clock distribution system into segments by introducing local clock buffers distributed throughout the scan chain. Each buffer segment independently manages clock signal distribution to its local region, replacing the monolithic external clock tree with modular, distributed clock segments that reduce overall complexity while enabling faster local scan operations
Solution Approach 2:
The patent introduces local clock buffers as intermediary elements between the external JTAG clock source and the scan chain flip-flops. These buffers act as mediators that receive the external clock signal and generate local clock signals at higher frequencies, thereby decoupling the scan chain speed from the external JTAG clock speed and reducing the complexity of direct external clock distribution
2Productivity
If a faster internal clock is used for the scan chain, then multiple internal scan operations can complete within a single external JTAG cycle, but additional clock distribution infrastructure is required
Solution Approach 1:
The patent implements self-service by enabling the scan chain to generate its own internal clock signals through the local buffers, which automatically oversample the external JTAG clock to produce faster internal clock frequencies. This self-generated clocking mechanism eliminates the need for separate external high-speed clock sources and reduces the overall clock distribution infrastructure complexity while significantly improving testing throughput
Data Source
AI summary
A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.