JTAG Shift Register Parallel Loading via Set and Reset Pins
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing boundary-scan test architectures, as defined by the JTAG standard, require a significant number of clock cycles to load an instruction into a shift register due to the limitation of loading only one bit per clock cycle, which increases the time required for a JTAG scan.
Innovation Solution
The introduction of additional input pins, specifically a set pin and a reset pin, allows for the simultaneous setting or resetting of all bits in a shift register based on the last bit of the instruction, reducing the number of clock cycles needed to load the instruction by removing continuous sequences of ones or zeros, thereby optimizing the loading process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the JTAG standard protocol is used to load data serially into a shift register, then the testing architecture remains compatible with existing standards, but the number of clock cycles required to load an instruction increases significantly
Solution Approach 1:
The patent applies preliminary action by detecting the value of the last bit of the instruction before the loading process begins. Based on this pre-detection, the system prepares the appropriate loading strategy (sequential or parallel) in advance, allowing the shift register to be loaded more efficiently without violating JTAG standard compatibility
Solution Approach 2:
The patent implements dynamics by making the data loading mechanism adaptive rather than fixed. The system dynamically switches between sequential loading (for instructions ending in 0) and parallel loading (for instructions ending in 1), allowing the loading process to optimize its speed based on the specific instruction being loaded while maintaining standard compliance
2Loss of time
If additional input pins are added to enable parallel loading of the shift register, then the number of clock cycles required to load an instruction is reduced, but the device complexity increases
Solution Approach 1:
The additional input pins serve multiple functions: they can load data in parallel when the last bit is 1, and the same pins can be used for sequential loading when the last bit is 0. This multi-functionality allows the system to achieve faster loading speeds without requiring completely separate hardware paths, thereby reducing the overall complexity increase
Solution Approach 2:
The patent applies local quality by providing different loading mechanisms for different parts of the instruction data based on the last bit value. Rather than uniformly increasing complexity for all data loading operations, the system only activates the parallel loading path when beneficial (when last bit is 1), keeping the architecture simple for the majority of cases
Data Source
AI summary
A method of loading a data string into a Joint Test Action Group (JTAG) shift register is provided. The method includes determining whether the last bit of the data string is equal to one or zero. In response to determining that the last bit is equal to one, the method includes simultaneously setting each flip-flop of the shift register to one, identifying first data string loading bits by removing, from the data string, the last bit and any other bits in a continuous sequence of bits, including the last bit, that are each equal to one, and sequentially loading the identified first data string loading bits into the shift register. A testing apparatus for performing the method and an enhanced JTAG interface are also provided. The method, testing apparatus, and enchanced JTAG interface may reduce the number of clock cycles required to load the shift register.