JTAG TAP Apparatus Data Verification via Host Comparison

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Solution Overview

Problem

Conventional JTAG test mechanisms require additional circuitry for data verification and CRC verification, increasing costs and implementation complexity, without effectively verifying data transmission accuracy between the JTAG host and TAP.

Innovation Solution

A JTAG TAP apparatus with a first and second data register, coupled between a JTAG host and memory interface, allows for direct comparison of data sent and received data, eliminating the need for on-chip CRC chips and reducing verification errors through a comparison circuit unit in the JTAG host.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If CRC verification code is added and CRC verification circuit is implemented within the target system to verify data downloading correctness, then data verification capability is improved, but circuit costs and implementation difficulty increase

Engineering Contradiction:

Improvedata verification capabilityVSAvoidcircuit costs and implementation difficulty

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the CRC verification function from the target system and relocates it to the JTAG host. The JTAG host generates CRC verification codes and performs verification, while the target system only needs to provide basic data transmission and storage capabilities. This extraction eliminates the need for complex CRC verification circuits in the target system, reducing its complexity while maintaining verification capability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a comparison register as an intermediary component between the data register and the JTAG host. This comparison register stores received data and enables the JTAG host to compare transmitted data with received data, providing a simple yet effective verification mechanism without requiring complex on-chip verification circuits.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If data comparison circuit and CRC verification circuit are added within the target system to verify data downloading, then verification completeness is improved, but circuit costs increase

Engineering Contradiction:

Improveverification completenessVSAvoidcircuit costs

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent removes the CRC verification circuit and data comparison circuit from the target system, relocating these functions to the JTAG host. The comparison register in the target system serves only as a simple storage buffer, while all complex verification operations are performed externally by the JTAG host, significantly reducing the quantity of circuit components required in the target system.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses the comparison register to store a copy of the received data, which is then compared by the JTAG host against the original transmitted data. This copying approach enables complete verification without requiring expensive dedicated verification circuits, as the comparison is performed using the host's existing processing capabilities.

Inventive Principle:

Principle #26Copying

3Measurement precision

If conventional JTAG verification method is used with on-chip CRC chips, then data transmission accuracy is improved, but verification error rate increases due to circuit complexity

Engineering Contradiction:

Improvedata transmission accuracyVSAvoidverification error rate

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent extracts the CRC chip functionality from the target system and implements it in the JTAG host software/firmware. This extraction eliminates potential hardware defects and timing issues associated with on-chip CRC chips, while maintaining the same level of data transmission accuracy through software-based verification.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements a feedback mechanism where the JTAG host continuously monitors data transmission by comparing transmitted data with received data stored in the comparison register. This feedback loop allows for real-time detection and correction of transmission errors, improving verification reliability while maintaining measurement precision through iterative verification.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11327115B2Scheme applied in JTAG TAP apparatus, JTAG host, and target system capable of achieving data verification as well as saving on-chip circuit costs

Publication Date: 2022.05.10 REALTEK SEMICON CORP

AI summary

A JTAG TAP apparatus coupled between a host and an interface circuit, which is coupled between a memory and the JTAG TAP apparatus, includes first pin, second pin, first data register, and second data register. The first data register stores data shifted in by the host via the first pin, the shifted in data is stored into a specific address of the memory via the interface circuit. The second data register stores read back data from the specific address of the memory via the interface circuit and outputs the read back data to the host via the second pin to make the host compare the shifted in data with the read back data to perform comparison test.