JTAG TAP Selection via Multiplexing and nTRST Pin

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Solution Overview

Problem

JTAG interfaces in integrated circuits often require additional pins for TAP selection, leading to increased latency during boundary scan testing and pin count inefficiencies, which are undesirable in certain scenarios.

Innovation Solution

A circuit design that couples test access port (TAP) signals to a JTAG interface without the need for a TAPSEL pin, using an nTRST pin and TMS pin to selectively control between testing and debugging TAPs, and employs multiplexing circuitry with glue logic to reduce latency and pin count, ensuring compliance with IEEE Standard 1149.1-2013.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a TAPSEL pin is added to select between testing and debugging TAPs, then TAP selection capability is improved, but pin count increases

Engineering Contradiction:

ImproveTAP selection capabilityVSAvoidpin count

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The nTRST pin is made multi-functional by having it serve both as a reset signal input for the debugging TAP and as a TAP selection control. When asserted, it selects the debugging TAP; when deasserted, it selects the testing TAP. This eliminates the need for a dedicated TAPSEL pin while maintaining full TAP selection capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the TAP selection function with the existing nTRST pin functionality. The selection logic merges the reset signal state (asserted/deasserted) with TAP selection (debugging/testing), so that a single pin controls both reset and selection, reducing overall pin count.

Inventive Principle:

Principle #5Merging (Combining)

2Quantity of substance

If testing and debugging TAPs are connected in series, then pin count is reduced, but latency increases during boundary scan testing

Engineering Contradiction:

Improvepin countVSAvoidboundary scan testing latency

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent implements dynamic TAP configuration where the connection topology between TAPs changes based on operational mode. Through multiplexing circuitry controlled by the nTRST pin state, the system dynamically switches between parallel configuration (for boundary scan testing with low latency) and selective configuration (for debugging operations), rather than using a fixed series connection.

Inventive Principle:

Principle #15Dynamics

3Ease of operation

If an extra pin is used for TAP selection, then TAP selection control is simplified, but device complexity increases

Engineering Contradiction:

ImproveTAP selection controlVSAvoidpin configuration complexity

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The system uses the existing nTRST pin state (asserted or deasserted) to automatically determine which TAP should be active. The selection logic is self-service in that it leverages the natural binary state of the reset signal to control TAP selection without requiring additional control pins or complex external selection circuitry.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS11041905B2Combinatorial serial and parallel test access port selection in a JTAG interface

Publication Date: 2021.06.22 STMICROELECTRONICS INT NV

AI summary

A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.