JTAG TAP Reset Circuit for Power-Cycle-Free Scan Exit
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Solution Overview
Problem
Existing methods for exiting scan test mode in system-on-a-chip devices require power cycling or an additional pin, leading to increased test time and cost due to reduced tester bandwidth and device area usage.
Innovation Solution
A reset circuit is integrated with a JTAG TAP to control the Test Control Registers (TCRs) using a combination of flip flops and logic gates, allowing user-controlled entry and exit from scan mode without power cycling or additional pins, by asserting a TCR reset signal based on the deassertion of scan enable and scan input signals during the capture phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power cycling is used to exit scan mode, then the TCR can be reset, but test time increases
Solution Approach 1:
The reset circuit is pre-configured with flip flops and logic gates that automatically detect when scan mode needs to be exited and generate the appropriate reset signal without requiring manual intervention or power cycling. The circuit is prepared in advance to perform the reset function based on specific signal conditions.
Solution Approach 2:
The reset circuit operates autonomously by monitoring the scan enable and scan input signals. When the conditions for exiting scan mode are met, the circuit automatically generates and applies the TCR reset signal without external intervention, making the system self-sufficient in managing mode transitions.
2Ease of operation
If an additional pin is added to reset TCR, then scan mode can be exited, but device area increases
Solution Approach 1:
The existing TDI and TMS pins are made multi-functional by using them both for scan testing operations and for triggering the reset function. The reset circuit interprets specific signal combinations on these pins as reset commands, eliminating the need for dedicated reset pins while maintaining full functionality.
Solution Approach 2:
The reset function is merged with the existing scan testing control logic. The flip flops and logic gates are integrated into the TAP structure, combining the reset mechanism with the scan enable and scan input signal handling, thereby reducing the overall pin count and device area.
3Ease of operation
If an additional pin is added to reset TCR, then scan mode can be exited, but tester bandwidth is reduced
Solution Approach 1:
The TDI and TMS pins serve dual purposes: they carry scan test data and control signals during normal testing operations, and they simultaneously provide the trigger signals for the reset function. This multi-functionality eliminates the need for additional pins that would consume tester bandwidth.
Solution Approach 2:
The reset trigger signals are merged with the existing scan test control signals. The logic circuitry combines the reset function with the scan enable and scan input signal processing, allowing the same physical pins to carry both testing and resetting functions without requiring separate dedicated pins.
Data Source
AI summary
A system for performing scan testing on a device core uses a test access port (TAP). The TAP includes a test clock (TCK) pin, a test data in (TDI) pin, and a test mode select (TMS) pin, along with a test control register (TCR) associated with it. The TCR is used to set a scan mode signal, which configures the scan flip flops within the device core for scan testing and performs the scan testing on the device core. The TCR can also be reset to exit the scan testing, with the reset being triggered by a reset circuit receiving the deassertion of both a scan enable (SE) signal and a scan input (SI) signal during the capture-phase of scan testing.