JTAG Test Interface Matrix for Memory Component Testing
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Solution Overview
Problem
The integration of non-volatile Flash memories in System-on-Chip (SoC) devices faces challenges as lithography nodes approach 28 nm, leading to physical limitations in on-board memory demand and inefficient testing interfaces, necessitating a new interface architecture that improves performance and testing efficiency.
Innovation Solution
A memory component with a JTAG test interface featuring a matrix-configured test register system, allowing for efficient connection with a host device or test machine, and utilizing a JTAG interface for both testing and control, enabling scalable memory arrays and secure testing protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-volatile Flash memories are integrated in SoC devices to meet on-board memory demand, then memory capacity is improved, but physical limitations are reached as lithography nodes approach 28 nm
Solution Approach 1:
The patent segments the memory interface into separate functional blocks: a first interface for normal data operations and a second interface for testing operations. This allows the memory component to be integrated in SoC while maintaining dedicated testing capabilities through separate contact pads and test registers, avoiding physical limitations of shared interfaces at advanced lithography nodes.
Solution Approach 2:
The patent introduces test registers as intermediary elements between the memory array and the testing machine. These test registers, organized in a matrix configuration with address selection, act as a mediator that enables efficient testing of memory components without requiring direct complex interconnections, thus overcoming physical integration limits.
2Reliability
If traditional testing interfaces are used for memory components in SoC, then testing capability is maintained, but testing efficiency is insufficient
Solution Approach 1:
The test interface is designed with multi-functionality: the same JTAG interface and test registers can be used for both factory testing and in-system testing of memory components within SoC. The test registers can be configured to perform different test operations, making the interface universal and highly efficient for various testing scenarios.
Solution Approach 2:
The patent organizes test registers in a matrix configuration with row and column addressing, adding a dimensional approach to test register organization. This matrix structure allows efficient selection and access of test registers, significantly improving testing efficiency compared to traditional linear or flat register arrangements.
3Productivity
If a new interface architecture is introduced to improve memory performance and testing efficiency, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent merges the testing functionality into the existing memory component structure by integrating test registers with the memory array. The test interface shares common infrastructure such as control logic and address decoders with the normal memory interface, combining multiple functions into a unified architecture that improves testing efficiency without proportionally increasing complexity.
Data Source
AI summary
A memory component comprises a memory unit including an array of memory cells, a controller of the memory unit, and a JTAG test interface including a plurality of contact pads adapted to connect the memory component with a host device and/or a test machine, wherein the test interface further comprises a plurality of test registers, which are configured to store the operating instructions for performing the test of the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. A related System-On-Chip device and a related method are further disclosed.