JTE Border Doping Layout for Stable SiC Reverse Blocking
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Solution Overview
Problem
High voltage semiconductor devices, particularly Silicon Carbide (SiC) products, face challenges in designing a robust termination area due to unoptimized dimensions, process variations, and passivation charges, leading to reduced reverse blocking capability, unstable ruggedness, and reliability issues.
Innovation Solution
The semiconductor device incorporates a junction termination extension (JTE) border with a first layer of one conductivity type and a second layer of a different conductivity type, where the second layer is located on top of the first layer, allowing for controlled depletion regions and reduced surface charge effects, along with floating JTE rings and a passivation layer to mitigate these issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a nitride-based passivation is used in the termination area, then surface protection and insulation are improved, but positive interface charges accumulate causing depletion regions that reduce reverse blocking capability and reliability
Solution Approach 1:
The patent extracts and removes the harmful positive interface charges from the termination area by implementing a dedicated charge compensation region with opposite polarity doping, thereby eliminating the depletion regions that would otherwise form under the passivation layer
Solution Approach 2:
The patent introduces an intermediary charge compensation region between the passivation layer and the active semiconductor structures. This intermediary region with opposite polarity doping serves to neutralize the interface charges, allowing the passivation layer to maintain its protective function without generating harmful depletion regions
2Reliability
If the termination area is designed to spread potential lines, then voltage distribution is improved, but process variations and unoptimized dimensions cause field crowding at weak spots
Solution Approach 1:
The patent applies local quality by creating regions with different doping characteristics within the termination area. Specifically, it implements charge compensation regions with opposite polarity doping adjacent to areas with standard doping, allowing each local region to perform its specific function: standard regions spread potential lines while compensation regions neutralize interface charges and prevent field crowding
3Reliability
If floating guard rings are used to spread equipotential lines, then voltage spreading is improved, but the structure complexity increases and process alignment requirements become more stringent
Solution Approach 1:
The patent merges the functions of voltage spreading and charge compensation into a unified termination area design. By integrating charge compensation regions directly into the termination structure with standard doping regions, it achieves equipotential line spreading without requiring separate floating guard rings, thereby reducing structural complexity and process alignment requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the semiconductor device's performance by reducing the impact of passivation charges, improving ruggedness, and providing more stable working conditions, thereby increasing the reliability and effectiveness of the termination area.
Implementation Method 1
a second layer of a second conductivity type different from the first conductivity type, wherein the second layer is located on top of the first layer
Implementation Method 2
Without wishing to be bound by theory, the inventors believe that a reduced effect of the abovementioned surface charges on the performance of the semiconductor device is achieved by the JTE border including a first layer of a first conductivity type and, located on top of this layer, a second layer of a second conductivity type
Data Source
AI summary
The present disclosure relates to a semiconductor device that includes a semiconductor body including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. An active area and a termination area adjacent the active area are arranged in the epitaxial layer. The termination area includes a junction termination extension (JTE) border of a first conductivity type. The JTE border includes a first layer of the first conductivity type, and a second layer of a second conductivity type different from the first conductivity type. The second layer is located on top of the first layer. The semiconductor substrate and the epitaxial layer have the second conductivity type.