JTE Top Surface Layout With Inverted Kao Rings for Field Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in effectively reducing the electric field at the critical interface region between the Junction Termination Extension (JTE) and the passivation stack, leading to reliability failures, low reverse blocking capability, and poor UIS ruggedness, especially in Silicon Carbide (SiC) devices.
Innovation Solution
The implementation of an 'inverted' Kao ring structure in the JTE region, created through an N+ area implant followed by a dry etch step, balances charge and distributes the electric field, enhancing the robustness of the termination against doping and charge variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard JTE termination structure is used, then device complexity is reduced, but electric field distribution is poor leading to reliability failures
Solution Approach 1:
The termination structure is segmented into multiple regions: the JTE region with P-type doping, recessed regions etched into the JTE, and N+ implant regions positioned in the mesa areas between recesses. This segmentation creates a more complex but reliable termination structure that better distributes the electric field.
Solution Approach 2:
Different regions of the termination structure are given different local properties: P-type doping in the JTE region, N+ implant in specific mesa regions, and recessed areas to modify field distribution. This local differentiation optimizes electric field control at critical interfaces.
2Reliability
If deeper JTE implants are implemented to improve termination, then reverse blocking capability improves, but manufacturing difficulty increases due to low diffusion coefficients
Solution Approach 1:
The N+ implant is applied preliminarily to the top surface of the JTE region before final passivation. This preliminary action creates a controlled charge distribution that compensates for interface traps and improves field distribution without requiring excessively deep JTE implants.
Solution Approach 2:
The doping parameters are optimized by introducing N+ implant with specific concentration and depth control at the top surface of the JTE. This parameter change allows achieving better termination performance without increasing the overall JTE implant depth, thus maintaining manufacturability.
3Reliability
If interface traps are reduced to improve termination efficiency, then charge accumulation decreases, but manufacturing precision requirements increase
Solution Approach 1:
The N+ implant acts as an intermediary layer between the JTE region and the passivation interface. It compensates for interface traps by providing opposite charge, thereby reducing charge accumulation effects without requiring perfect interface quality control.
Solution Approach 2:
The termination structure uses a composite doping approach combining P-type JTE region with N+ implant regions. This composite structure creates a more robust termination that is less sensitive to interface trap variations, improving breakdown voltage stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces electrical field peaks at the JTE surface, improves the control of lateral doping, and enhances the reliability and stability of the semiconductor device under high bias and temperature conditions.
Implementation Method 1
implant of a semiconductor body
Implementation Method 2
dry etch step
Data Source
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AI summary
The present disclosure presents a semiconductor device including a semiconductor body, wherein the semiconductor body includes one or more recessed regions in a P doped Junction Termination Extension, JTE, region, wherein a depth of the recessed regions is smaller than a depth of the JTE region, and an N+ implant at a top surface of the JTE region, such that the N+ implant forms a part of mesa regions in between the recessed regions. A method of manufacturing such semiconductor device is also presented.