Jump Double Indirect Instruction Pipeline Optimization
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Solution Overview
Problem
Deeply pipelined digital processors face significant performance penalties due to frequent jump instructions, as they require clearing and re-executing pipeline stages, which is exacerbated by the limitations of existing branch prediction techniques.
Innovation Solution
The introduction of a 'jump double indirect' (JDI) instruction and associated control unit that precomputes and stores target addresses in a memory table, allowing the processor to prefetch future addresses and modify pointers to optimize jump operations, thereby reducing pipeline bubbles and enhancing prediction accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor uses deeply pipelined architecture to achieve high speed operation, then the processing throughput is improved, but the performance penalty increases when jump instructions are executed due to pipeline clearing requirements
Solution Approach 1:
The branch predictor performs preliminary actions by predicting jump targets before the jump instruction completes execution through the pipeline. The system pre-calculates and stores target addresses in a memory table, allowing the pipeline to continue fetching instructions at the predicted target address without waiting for the jump to be resolved, thus avoiding pipeline stalls while maintaining deep pipelining benefits
2Device complexity
If branch prediction is not utilized, then the processor architecture remains simple, but the pipeline must be cleared and re-executed at each jump instruction, causing severe performance penalties
Solution Approach 1:
The invention introduces a memory table as an intermediary structure between the branch predictor and the instruction pipeline. The memory table stores pre-computed target addresses and serves as a buffer that decouples the complex prediction logic from the simple pipeline fetch mechanism, allowing accurate prediction without significantly increasing pipeline complexity
Solution Approach 2:
The invention extracts the complex branch prediction logic from the main instruction pipeline by implementing a separate memory table for storing target addresses. This separation allows the pipeline to remain relatively simple while delegating the complex prediction task to a dedicated prediction unit that operates in parallel, fetching predicted targets independently of the main execution flow
Data Source
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AI summary
Methods and apparatus are provided for performing a jump operation in a pipelined digital processor. The method includes writing target addresses of jump instructions to be executed to a memory table, detecting a first jump instruction being executed by the processor, the first jump instruction referencing a pointer to a first target address in the memory table, the processor executing the first jump instruction by jumping to the first target address and modifying the pointer to point to a second target address in the memory table, the second target address corresponding to a second jump instruction. The execution of the first jump instruction may include prefetching at least one future target address from the memory table and writing the future target address in a local memory. The second target address may be accessed in the local memory in response to detection of the second jump instruction.