Jump Instruction Translation State Change

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Solution Overview

Problem

Conventional computer systems require multiple, inefficient steps for managing translation state changes during interrupts, including identity mapping of instruction addresses, which consumes resources and slows down execution.

Innovation Solution

A method that performs a jump and translation state change simultaneously, using a jump instruction to initiate and complete the state change, storing the return address and original translation state in registers, eliminating the need for identity mapping and optimizing memory management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple separate steps are used for translation state change and jump operations, then translation state management is achieved, but execution speed decreases and resource consumption increases

Engineering Contradiction:
Improvetranslation state management precisionVSAvoidexecution speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines the translation state change operation and the jump operation into a single atomic instruction execution. When a jump instruction is executed, the translation state change and the jump to the target address occur simultaneously in one step, eliminating the need for separate execution steps. This merging of operations maintains precise translation state management while significantly improving execution speed by reducing the number of instruction cycles required.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If identity mapping of instruction addresses is used during translation state change, then translation correctness is ensured, but MMU translation resources are consumed and execution is slowed

Engineering Contradiction:
Improvetranslation correctnessVSAvoidMMU translation resource consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent performs the translation state change as a preliminary action that is intrinsically linked to the jump instruction execution. By changing the translation state before the jump instruction completes its execution, the system ensures that subsequent memory access instructions will use the correct translation state without requiring identity mapping. This preliminary state change eliminates the need for resource-consuming identity mapping operations while maintaining translation correctness.

Inventive Principle:
Principle #10Preliminary action

3Stability of the object's composition

If separate wait instructions are used to confirm translation state change completion, then translation state stability is ensured, but execution time increases

Engineering Contradiction:
Improvetranslation state stabilityVSAvoidexecution time
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The patent merges the translation state change confirmation with the jump instruction execution itself. The translation state change is performed atomically as part of the jump instruction, and the completion of the jump instruction inherently confirms that the translation state change has been successfully applied. This eliminates the need for separate wait instructions that would otherwise be required to verify translation state stability, thereby reducing execution time while maintaining state stability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7934073B2Method for performing jump and translation state change at the same time
Publication Date: 2011.04.26 ANDES TECH
  • US7934073B2 patent drawing
  • US7934073B2 patent drawing
  • US7934073B2 patent drawing

AI summary

A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.