Jump-Controlled Pipeline Processor Without Bubble Cycles
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Solution Overview
Problem
Pipeline bubbles occur in RISC processors due to wasted clock cycles when executing jump instructions, reducing processing performance.
Innovation Solution
A processor with an instruction fetcher, decoder, and executer connected by a table and pipeline controller that sets jump destination addresses and instructions directly into the program counter, allowing parallel execution of consecutive instructions without fetching from memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipeline processing is used to execute instructions in parallel stages, then processing speed is improved, but jump instructions cause pipeline bubbles that waste clock cycles
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing jump destination addresses in a dedicated jump address storage unit before the jump instruction is executed. When a jump instruction is detected in the instruction fetch stage, the system can immediately retrieve the pre-calculated destination address, avoiding pipeline bubbles and maintaining continuous instruction flow without wasting clock cycles.
2Adaptability or versatility
If jump instructions are executed by updating program counter after decoding, then control flow changes are achieved, but instruction fetch and decode stages execute wastefully before the jump
Solution Approach 1:
The patent segments the instruction processing by separating jump instruction handling from the normal instruction flow. A jump detection unit specifically identifies jump instructions during the fetch stage, and a jump address storage unit stores pre-calculated destinations. This segmentation allows the system to bypass the normal decode-and-execute sequence for jump instructions, directly updating the program counter with the pre-prepared destination address, thus preventing wasteful execution of subsequent instructions.
3Stability of the object's composition
If the program counter is updated sequentially for each instruction, then instruction ordering is maintained, but jump destinations require fetching from wrong addresses
Solution Approach 1:
The patent introduces a jump address storage unit as an intermediary between the jump instruction and the program counter. This intermediary stores pre-calculated jump destination addresses, allowing the system to maintain sequential processing for most instructions while correctly redirecting to jump targets when needed. The intermediary resolves the conflict between maintaining instruction sequence integrity and correctly implementing control flow changes by providing the correct destination address without disrupting the overall sequential flow.
Data Source
AI summary
Provided is a processor controlling pipeline processing to avoid the occurrence of pipeline bubbles as much as possible even when executing jump instruction. The present processor executes pipeline processing in which: an instruction fetcher fetching a machine-language instruction based on a memory address set in a program counter; a decoder decoding the machine-language instruction output from the instruction fetcher into control information; and an executer executing the control information output from the decoder, are connected, and the present processor comprises: a table describing a head address and a head machine-language instruction for each destination of jump; and a pipeline controller setting, when the executer executing a control information of a jump, an address specifying a second machine-language instruction at a destination of the jump into the program counter by using the table, while to input a head machine-language instruction at the destination of the jump to the decoder.