Jumper Gate Layout for Nanowire IC Routing Relief
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to constraints on lithographic processes, particularly in maintaining mobility improvement and short channel control as device dimensions approach the 10 nanometer node, leading to issues with critical dimension and spacing between features, which complicates routing and impacts performance.
Innovation Solution
The implementation of jumper gates in integrated circuit structures allows for connections between diffusion contacts and gates without requiring back-end metal routing resources, using a process that cuts and fills nanowires or ribbons with gate material to short the intrinsic silicon ribbons to the gate, enabling connections in gate-all-around devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lithographic processes are used to pattern multi-gate transistors at smaller dimensions, then device density increases, but the spacing between features and critical dimension control deteriorate
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional multi-gate structures (tri-gate, gate-all-around). By stacking nanowires vertically and wrapping gates around channels in 3D space, the design moves beyond conventional lithographic limits, achieving higher effective density without proportionally reducing lateral feature sizes that lithography can control.
Solution Approach 2:
The gate structure is nested around the channel in multiple dimensions - gates wrap around nanowire channels from top, bottom, and sidewalls (gate-all-around configuration). This nested arrangement maximizes the gate's control over the channel while maintaining compact lateral footprints, effectively increasing device density without compromising dimensional control.
2Productivity
If device dimensions are scaled down to increase the number of devices per chip, then capacity increases, but mobility improvement and short channel control deteriorate
Solution Approach 1:
By stacking multiple nanowire channels vertically and providing gate control from all directions (top, bottom, sidewalls), the structure achieves better electrostatic control and carrier mobility without further lateral scaling. The 3D configuration allows the gate to control the channel more effectively at smaller dimensions, maintaining reliability while increasing device count through vertical stacking.
Solution Approach 2:
The patent employs composite material structures including silicon-germanium (SiGe) source/drain regions combined with silicon nanowire channels, and high-k dielectric gate insulators with metal gate electrodes. These composite materials provide strain engineering to enhance carrier mobility and improved electrostatic control, maintaining device performance as dimensions scale.
3Adaptability or versatility
If back-end metal routing resources are used to connect diffusion contacts to gates, then routing flexibility is maintained, but device complexity and capacitance increase
Solution Approach 1:
The jumper gate structure merges the gate electrode with the interconnect function by extending the gate material to form direct electrical connections between diffusion contacts and gate terminals. This eliminates the need for separate metal routing layers (Metal1, Metal0) for these specific connections, reducing overall interconnect complexity and parasitic capacitance while maintaining routing flexibility through the gate's inherent connectivity.
Data Source
AI summary
Jumper gates for advanced integrated circuit structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowire segments. A second vertical stack of horizontal nanowire segments is spaced apart from the first vertical stack of horizontal nanowire segments. A conductive structure is laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments. A first source or drain structure is coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure. A second source or drain structure is coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.