Junction Dopant Profile Control via Atomic Layer Epitaxy
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Solution Overview
Problem
Existing methods for manufacturing bipolar transistors face challenges in controlling the dopant concentration profile and in-diffusion depth at the emitter-base interface, particularly due to high thermal budgets in BiCMOS processes, leading to suboptimal device characteristics.
Innovation Solution
A method involving Atomic Layer Epitaxy (ALE) and rapid thermal treatment is used to control the dopant concentration profile by creating a steep, abrupt profile at the emitter-base junction, utilizing n-type dopants like arsenic and p-type dopants like boron, with a sequence of epitaxial growth and precursor deposition to exceed solid solubility limits, and performing a rapid thermal anneal to optimize dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a spike anneal is performed after emitter layer deposition to activate CMOS junctions, then CMOS junction activation is achieved, but the high thermal budget adversely impacts bipolar device characteristics
Solution Approach 1:
The patent applies local quality by creating a highly doped region (δ-doping sheet) at the emitter-base interface with dopant concentration exceeding solid solubility limits. This localized high-dopant region enables precise control of the dopant profile at the critical junction interface while allowing the rest of the emitter to maintain optimal doping levels for bipolar operation, thus resolving the conflict between CMOS activation requirements and bipolar device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of the dopant profile and in-diffusion depth, improving bipolar transistor performance by reducing parasitic resistance and enhancing high-frequency performance while being compatible with conventional CMOS flows.
Implementation Method 1
depositing by Atomic Layer Epitaxy a monolayer of a precursor suitable to form the second dopant on the first semiconductor material
Implementation Method 2
performing a rapid thermal treatment, wherein said rapid thermal treatment is performed after the step of forming a second semiconductor material
Implementation Method 3
thereby incorporating the second dopant in substitutional sites in the second semiconductor material
Data Source
AI summary
The present invention relates to a method for manufacturing a junction with a controlled dopant (concentration) profile comprising (or consisting of) the steps of: - forming a first semiconductor material comprising a first dopant having a first concentration and thereupon - forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and - depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction.