Junction Edge Termination Structure for Stable Breakdown Voltage
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Solution Overview
Problem
The reliability and consistency of high-voltage semiconductor devices are compromised due to surface charges affecting the electric field distribution at the junction edge termination region, leading to reduced breakdown voltage and device lifetime.
Innovation Solution
A semiconductor device with a junction edge termination region comprising a semiconductor substrate, an epitaxial layer, floating regions, an insulator layer, and field limiting rings (FLRs) is designed, where the floating regions absorb electric flux lines to disperse the applied voltage and reduce surface electric field peaks, thereby minimizing the impact of surface charges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a field limiting ring (FLR) technique is employed to improve breakdown voltage, then the electric field at the surface of the main junction is decreased, but surface charges are easily introduced in the manufacturing process which changes the electric field distribution and lowers reliability and consistency
Solution Approach 1:
An insulator layer is introduced as an intermediary between the surface and the semiconductor structures. This insulator layer prevents surface charges from forming or accumulating, thereby eliminating the harmful effect of surface charges on electric field distribution while maintaining the voltage-sustaining capability provided by the FLR structure
Solution Approach 2:
The harmful factor (surface charges) is extracted or removed from the system by applying an insulator layer that prevents charge accumulation. This extraction approach directly addresses the reliability issue without compromising the breakdown voltage enhancement achieved through the FLR technique
2Strength
If the voltage withstanding level of the devices is increased, then the breakdown voltage is improved, but the design requirements for the size and doping of the FLRs become more and more stringent
Solution Approach 1:
The insulator layer changes the physical parameters of the surface environment, effectively decoupling the surface charge formation from the semiconductor structures. This parameter change allows the FLR design to focus solely on voltage withstanding requirements without the additional constraint of managing surface charge effects, thereby simplifying the overall design
3Ease of manufacture
If surface charges are present in the manufacturing process, then the electric field distribution at the junction edge is changed, but this results in change of breakdown voltage and lowered reliability and consistency
Solution Approach 1:
The insulator layer serves as a protective intermediary during manufacturing, preventing surface charge accumulation that would otherwise occur during processing. This intermediary layer maintains consistent electric field distribution and breakdown voltage characteristics throughout the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability and consistency of the semiconductor device by reducing the influence of surface charges on breakdown voltage and preventing hot carrier injection into the oxidation layer, leading to improved voltage sustainability and extended device lifetime.
Implementation Method 1
floating regions absorb electric flux lines to disperse the applied voltage and reduce surface electric field peaks
Implementation Method 2
preventing hot carrier injection into the oxidation layer
Data Source
AI summary
A semiconductor device and a junction edge region thereof. The junction edge region comprises a semiconductor substrate and an epitaxial layer above said substrate, the semiconductor substrate and the epitaxial layer being in a laminated structure and of the same conductor type; several floating regions spaced apart are provided between the semiconductor substrate and the epitaxial layer, a transition region is provided on the surface of the epitaxial layer adjacent to an active region portion, and the semiconductor substrate is additionally provided with a first semiconductor region.