Junctionless Semiconductor Buried Gate Leakage Reduction
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Solution Overview
Problem
Conventional semiconductor devices with buried gates face challenges in reducing area occupancy due to horizontal channel transistors and suffer from irregular retention characteristics caused by overlapping gate and source/drain regions, leading to variations in cell performance.
Innovation Solution
A junctionless semiconductor device is developed with a buried gate structure where the same type of impurities are implanted into the source, drain, and body, eliminating the PN junction and allowing current to flow selectively, and featuring a fin structure with a buried insulation film to improve uniformity and reduce Gate Induced Drain Leakage (GIDL).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a horizontal channel region transistor is used, then the transistor can be manufactured with conventional processes, but the overall area of the semiconductor device increases substantially
Solution Approach 1:
The patent transitions from a planar horizontal channel structure to a vertical channel structure by etching recesses into the semiconductor substrate. The channel region extends vertically beneath the gate electrode, utilizing the third dimension (depth) to achieve higher integration density while maintaining compatibility with conventional manufacturing processes
2Productivity
If the gate overlaps with the source/drain region in a buried gate structure, then the transistor can be formed with vertical channel, but Gate Induced Drain Leakage (GIDL) characteristics change and retention characteristics become irregular
Solution Approach 1:
The patent applies different doping types to different regions: P-type impurities are implanted into the channel region and N-type impurities into the source/drain regions (or vice versa), creating localized electrical properties that prevent gate overlap while maintaining vertical channel structure. This local differentiation of material properties resolves the GIDL and retention issues
Solution Approach 2:
The patent changes the electrical parameters by implanting opposite-type impurities in adjacent regions, which modifies the electrical characteristics to eliminate gate overlap effects. This parameter change approach transforms the physical structure to achieve uniform retention characteristics across all cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances operational characteristics by reducing leakage current and ensuring uniform doping, thereby improving retention and current flow, leading to more consistent performance across semiconductor cells.
Implementation Method 1
implanting the same type of impurities into a source, a drain and an active region
Data Source
AI summary
A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current.